3.4 CPU Reset Extension

The DSU module on the device has the CPU Reset extension feature that allows it to connect a debugger while the CPU is on Reset. This is also known as cold-plugging or, also, a core-hold Reset. Refer to the PIC32CX-BZ6 and PIC32WM-BZ6 Family Data Sheet.

This feature requires the debugger to control the level of SWCLK and MCLR pins. The CPU Reset extension is detected on an MCLR release event when SWCLK is low.

The main usage is to avoid executing potentially corrupted code at boot and allow a safe way to connect to a device without any assumption on its current state. The debugger can read/write memory and peripherals without the CPU interference.

Note: After the initial connect sequence, the debugger must release the CPU Reset extension to write to memory located outside the CPU (in other words, SRAM, Flash and peripherals) using MEM-AP. When the CPU is held in the Reset extension phase, the CPU Reset Extension (bit 1) of the Status A register (STATUSA.CRSTEXT) @0x4100_0101 of the DSU module is set. To release the CPU, write a 1 to STATUSA.CRSTEXT. STATUSA.CRSTEXT will, then, be set to 0. Writing a 0 to STATUSA.CRSTEXT has no effect. To keep the CPU from executing the user code, the debugger can rely on the Reset vector catch.