2.3 ADC Clock and Conversion Timing

The ADC uses the CLK_PER peripheral clock and has an internal prescaler to generate the ADC clock source CLK_ADC with a frequency between 50 kHz and 1.5 MHz for maximum resolution. If a lower resolution than 10 bits is selected, the input clock frequency to the ADC can be higher than 1.5 MHz to get a higher sample rate. The prescaling is selected by writing to the Prescaler bits (PRESC) in the Control C register (ADC.CTRLC).

When a conversion is initiated, the conversion starts at the following rising edge of the CLK_ADC clock cycle. The prescaler is kept in reset as long as there is no ongoing conversion. This assures a fixed delay from the trigger to the actual start of a conversion in CLK_PER cycles as $\mathrm{StartDelay}=\frac{{\mathrm{PRESC}}_{\mathrm{factor}}}{2}+2$.

A normal conversion takes 13 CLK_ADC cycles. The actual Sample-and-Hold takes place two CLK_ADC cycles after the start of a conversion.

Both sampling time and sampling length can be adjusted by using the Sample Delay bit field in the Control D (ADC.CTRLD) and the Sample Length bit field in the Sample Control register (ADC.SAMPCTRL). Both of these control the ADC sampling time in a number of CLK_ADC cycles. Total sampling time is given by:

$\mathrm{SampleTime}=\frac{(2+\text{SAMPDLY}+\text{SAMPLEN})}{f_{\text{CLK\_ADC}}}$.

In Free-Running mode, the sampling rate R_S is calculated by:

$\mathrm{SampleRate}=\frac{f_{\text{CLK\_ADC}}}{(13+\text{SAMPDLY}+\text{SAMPLEN})}$