4.2.2 Dual-Core Device Support

The MPLAB XC8 C Compiler supports dual-core devices in the AVR SD family.

These devices execute code on both cores simultaneously, comparing the results of each core to ensure consistent operation. The devices implement ECC (Error Correction Code) RAM, which can detect and correct some forms of data corruption. Multi-level traps indicate critical failures, such as a core execution mismatch, which will reset the device, as well as non-critical failures, such as invalid opcodes or ECC error, which can be masked by the programmer. A command line option is automatically set by the DFPs for dual-core devices, allowing the compiler to take into account all these special features when building project code.

Because of the devices' single-level pipelining and invalid opcode traps, there must always be a valid instruction after the last "real" instruction that is executed; otherwise fetching and decoding the next program memory location will cause a trap. For these devices, the linker automatically adds a nop instruction at the end of every code section that isn't immediately followed by another code section. It will add this instruction for all code section it allocates. To reduce the number of nop instructions required, the compiler will refrain from placing code and data in the same section, which might otherwise be performed, for example, when encoding jump tables.

As ECC errors can occur before program execution reaches the main() function, the startup code disables interrupts and masks non-critical traps immediately after Reset. This prevents user trap handling code executing before the runtime startup code has initialized the execution environment.