29.3.2.3 Truth Table Inputs Selection

Input Overview

The inputs can be individually:

  • Masked
  • Driven by peripherals:
    • Analog comparator output (AC)
    • Timer/Counters waveform outputs (TC)
  • Driven by internal events from Event System
  • Driven by other CCL sub-modules
The Input Selection for each input y of LUT n is configured by writing the Input y Source Selection bit in the LUT n Control x=[B,C] registers:
  • INSEL0 in CCL.LUTnCTRLB
  • INSEL1 in CCL.LUTnCTRLB
  • INSEL2 in CCL.LUTnCTRLC

Internal Feedback Inputs (FEEDBACK)

When selected (INSELy=FEEDBACK in CCL.LUTnCTRLx), the Sequential (SEQ) output is used as input for the corresponding LUT.

The output from an internal sequential module can be used as input source for the LUT, see the figure below for an example for LUT0 and LUT1. The sequential selection for each LUT follows the formula:

IN [ 2N ] [ i ] = SEQ [ N ]
IN [ 2N+1 ] [ i ] = SEQ [ N ]

With N representing the sequencer number and i=0,1 representing the LUT input index.

For details, refer to 29.3.2.6 Sequential Logic.

Figure 29-2. Feedback Input Selection

Linked LUT (LINK)

When selecting the LINK input option, the next LUT's direct output is used as the LUT input. In general, LUT[n+1] is linked to the input of LUT[n]. As example, LUT1 is the input for LUT0.

Figure 29-3. Linked LUT Input Selection

Internal Events Inputs Selection (EVENT)

Asynchronous events from the Event System can be used as input to the LUT. Two event input lines (EVENT0 and EVENT1) are available, and can be selected as LUT input. Before selecting the EVENT input option by writing to the LUT CONTROL A or B register (CCL.LUTnCTRLB or LUTnCTRLC), the Event System must be configured.

I/O Pin Inputs (I/O)

When selecting the I/O option, the LUT input will be connected to its corresponding I/O pin. Refer to the I/O Multiplexing section for more details about where the LUTnINy is located.

Figure 29-4. I/O Pin Input Selection

Peripherals

The different peripherals on the three input lines of each LUT are selected by writing to the respective LUT n Input y bit fields in the LUT n Control B and C registers:
  • INSEL0 in CCL.LUTnCTRLB
  • INSEL1 in CCL.LUTnCTRLB
  • INSEL2 in CCL.LUTnCTRLC