21.3.3.4.4 Dual-Slope PWM

For dual-slope PWM generation, the period (T) is controlled by TCAn.PER, while the values of TCAn.CMPn control the duty-cycle of the WG output.

The figure below shows how for dual-slope PWM the counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. The waveform generator output is set on BOTTOM, cleared on compare match when up-counting, and set on compare match when down-counting.

Figure 21-11. Dual-Slope Pulse-Width Modulation

Using dual-slope PWM results in a lower maximum operation frequency compared to the single-slope PWM operation.

The period register (TCAn.PER) defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER=0x0003), and the maximum resolution is 16 bits (TCAn.PER=MAX).

The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):

R PWM_DS = log PER + 1 log 2

The PWM frequency depends on the period setting (TCAn.PER), the peripheral clock frequency (fCLK_PER), and the prescaler divider used (CLKSEL in TCAn.CTRLA). It is calculated by the following equation:

f PWM_DS = f CLK_PER 2 N ⋅ PER

N represents the prescaler divider used.