31.5.17 Calibration
| Name: | CALIB |
| Offset: | 0x16 |
| Reset: | 0x01 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DUTYCYC | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 1 |
Bit 0 – DUTYCYC Duty Cycle
This bit determines the duty cycle of the ADC clock.
ADCclk > 1.5 MHz requires a minimum operating voltage of 2.7V
| Value | Description |
|---|---|
| 0 | 50% Duty Cycle must be used if ADCclk > 1.5 MHz |
| 1 | 25% Duty Cycle (high 25% and low 75%) must be used for ADCclk ≤ 1.5 MHz |