6.2 CONFIG2

Configuration Word 2

Note:

The DEBUG bit is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit needs to be maintained as a ‘1’.
The higher-voltage selection is recommended for operations at or above 16 MHz.
When enabled, the Brown-out Reset voltage (V_BOR) is set by the BORV bit.

Name:	CONFIG2
Offset:	0x8008


Bit	15	14	13	12	11	10	9	8
			DEBUG	STVREN	PPS1WAY	ZCD	BORV	DATCAUTOEN
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			1	1	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	BOREN[1:0]			WDTE[1:0]		PWRTS[1:0]		MCLRE
Access	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Reset	1	1		1	1	1	1	1

Bit 13 – DEBUG Debugger Enable⁽¹⁾

Value	Description
1	Background debugger disabled
0	Background debugger enabled

Bit 12 – STVREN Stack Overflow/Underflow Reset Enable

Value	Description
1	Stack Overflow or Underflow will cause a Reset
0	Stack Overflow or Underflow will not cause a Reset

Bit 11 – PPS1WAY PPSLOCKED One-Way Set Enable

Value	Description
1	The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCKED is set, all future changes to PPS registers are prevented
0	The PPSLOCKED bit can be set and cleared as needed (an unlocking sequence is required)

Bit 10 – ZCD Zero Cross Detect Disable

Value	Description
1	ZCD disabled, ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0	ZCD always enabled, PMDx [ZCDMD] bit is ignored

Bit 9 – BORV Brown-out Reset (BOR) Voltage Selection⁽²⁾

Value	Description
1	Brown-out Reset voltage (V_BOR) set to 1.9V
0	Brown-out Reset voltage (V_BOR) set to 2.65V

Bit 8 – DATCAUTOEN DAC Output Buffer Automatic Range Select Enable

Value	Description
1	Automatic range selection disabled; DAC Output Buffer range is determined by DACxCON
0	Automatic range selection enabled

Bits 7:6 – BOREN[1:0] Brown-out Reset (BOR) Enable⁽³⁾

Value	Description
11	Brown-out Reset enabled, SBOREN bit is ignored
10	Brown-out Reset enabled while running, disabled in Sleep; SBOREN bit is ignored
01	Brown-out Reset enabled according to SBOREN
00	Brown-out Reset disabled

Bits 4:3 – WDTE[1:0] Watchdog Timer Enable

Value	Description
11	WDT enabled regardless of Sleep; SEN bit of WDTCON is ignored
10	WDT enabled while Sleep = `0`, disabled when Sleep = `1`; SEN bit of WDTCON is ignored
01	WDT enabled/disabled by the SEN bit of WDTCON
00	WDT disabled, SEN bit of WDTCON is ignored

Bits 2:1 – PWRTS[1:0] Power-Up Timer (PWRT) Selection

Value	Description
11	PWRT disabled
10	PWRT is set at 64 ms
01	PWRT is set at 16 ms
00	PWRT is set at 1 ms

Bit 0 – MCLRE Master Clear (MCLR) Enable

Value	Name	Description
x	If LVP = `1`	MCLR pin is MCLR
1	If LVP = `0`	MCLR pin is MCLR
0	If LVP = `0`	MCLR pin function is port-defined function

The DEBUG bit is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit needs to be maintained as a ‘1’. The higher-voltage selection is recommended for operations at or above 16 MHz. When enabled, the Brown-out Reset voltage (VBOR) is set by the BORV bit.