38.3.1 Supply Voltage

Table 38-1. 
PIC18LF27/47K40 only
Standard Operating Conditions (unless otherwise stated)
Param. No.Sym.CharacteristicMin.Typ.†Max.UnitsConditions
Supply Voltage
D002VDD

1.8

—

3.6

V

FOSC ≤ 16 MHz

2.5

—

3.6

V

FOSC > 16 MHz

3.0

—

3.6

V

FOSC > 32 MHz
RAM Data Retention(1)
D003VDR1.5

—

—

V

Device in SLEEP mode
Power-on Reset Release Voltage(2)
D004VPOR

—

1.6

—

V

BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005VPORR

—

0.8

—

V

BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006SVDD0.05

—

—

V/msBOR or LPBOR disabled(3)

Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
  2. See the following figure, POR and POR REARM with Slow Rising VDD.
  3. Please see Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low-Power Brown-out Reset Specifications for BOR and LPBOR trip point information.
PIC18F27/47K40 only
Standard Operating Conditions (unless otherwise stated)
Param. No.Sym.CharacteristicMin.Typ.†Max.UnitsConditions
Supply Voltage
D002AVDD

2.3

—

5.5

V

FOSC ≤ 16 MHz

2.5

—

5.5

V

FOSC > 16 MHz

3.0

—

5.5

V

FOSC > 32 MHz
RAM Data Retention(1)
D003AVDR1.7

—

—

V

Device in SLEEP mode
Power-on Reset Release Voltage(2)
D004AVPOR

—

1.6

—

V

BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005AVPORR

—

1.5

—

V

BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006ASVDD0.05

—

—

V/msBOR or LPBOR disabled(3)

Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
  2. See the following figure, POR and POR REARM with Slow Rising VDD.
  3. Please see Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and Low-Power Brown-out Reset Specifications for BOR and LPBOR trip point information.
Figure 38-3. POR and POR Rearm with Slow Rising VDD
Note:
  1. When NPOR is low, the device is held in Reset.
  2. TPOR 1 µs typical.
  3. TVLOW 2.7 µs typical.