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20.14.4 TMRxGATE Timer Gate Source
Selection Register Name: TMRxGATE Offset: 0xFD1,0xFCB,0xFC5
Bit 7 6 5 4 3 2 1 0 GSS[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0
Bits 3:0 – GSS[3:0] Timer Gate Source Selection
bits
Table 20-5. Timer Gate Signal Selection GSS Gate Source Timer1 Timer3 Timer5 1111Reserved Reserved Reserved 1110ZCDOUT ZCDOUT ZCDOUT 1101CMP2OUT CMP2OUT CMP2OUT 1100CMP1OUT CMP1OUT CMP1OUT 1011PWM4OUT PWM4OUT PWM4OUT 1010PWM3OUT PWM3OUT PWM3OUT 1001CCP2OUT CCP2OUT CCP2OUT 1000CCP1OUT CCP1OUT CCP1OUT 0111TMR6OUT
(post-scaled) TMR6OUT
(post-scaled) TMR6OUT
(post-scaled) 0110TMR5
overflow TMR5
overflow Reserved 0101TMR4OUT
(post-scaled) TMR4OUT
(post-scaled) TMR4OUT
(post-scaled) 0100TMR3
overflow Reserved TMR3
overflow 0011TMR2OUT
(post-scaled) TMR2OUT
(post-scaled) TMR2OUT
(post-scaled) 0010Reserved TMR1
overflow TMR1
overflow 0001TMR0
overflow TMR0
overflow TMR0
overflow 0000Pin selected by
T1GPPS Pin selected by
T3GPPS Pin selected by
T5GPPS
Reset States: POR/BOR = 0000 All Other Resets = uuuu
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