23.12.1 PWMxDC
| Name: | PWMxDC |
| Offset: | 0xFA3,0xFA0 |
PWM Duty Cycle Register
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DCH[7:0] | |||||||||
| Access | |||||||||
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DCL[1:0] | |||||||||
| Access | |||||||||
| Reset | x | x | |||||||
Bits 15:8 – DCH[7:0] PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle.
| Reset States: |
|
Bits 7:6 – DCL[1:0] PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle.
| Reset States: |
|