2.3 Details on Individual Family Members
Devices in the PIC18(L)F27/47K40 family are available in 28/40/44-pin packages. The block diagram for this device is shown in the Figure 2-1.
The devices have the following differences:
- Program Flash Memory
- Data Memory SRAM
- Data Memory EEPROM
- Analog-to-Digital (A/D) channels
- I/O ports
- Enhanced USART
- Input Voltage Range/Power Consumption
All other features for devices in this family are identical. These are summarized in the following Device Features table.
The pinouts for all devices are listed in the pin summary tables.
| Features | PIC18(L)F27K40 | PIC18(L)F47K40 |
|---|---|---|
| Program Memory (Bytes) |
131072 |
131072 |
| Program Memory (Instructions) |
65536 |
65536 |
| Data Memory (Bytes) |
3720 |
3720 |
| Data EEPROM Memory (Bytes) |
1024 |
1024 |
| I/O Ports | A,B,C,E(1) |
A,B,C,D,E(1) |
| Capture/Compare/PWM Modules (CCP) | 2 | 2 |
| 10-Bit Pulse-Width Modulator (PWM) | 2 | 2 |
| 10-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator | 4 internal 24 external | 4 internal 35 external |
| Packages | 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN |
40-pin PDIP 40-pin UQFN 44-pin QFN 44-pin TQFP |
| Interrupt Sources | 36 | |
| Timers (16-/8-bit) | 4/3 | |
| Serial Communications | 2
MSSP, 2 EUSART | |
| Enhanced Complementary Waveform Generator (ECWG) | 1 | |
| Zero-Cross Detect (ZCD) | 1 | |
| Data Signal Modulator (DSM) | 1 | |
| Peripheral Pin Select (PPS) | Yes | |
| Peripheral Module Disable (PMD) | Yes | |
| 16-bit CRC with NVMSCAN | Yes | |
| Programmable High/Low-Voltage Detect (HLVD) | Yes | |
| Programmable Brown-out Reset (BOR) | Yes | |
| Resets (and Delays) | POR, BOR, RESET Instruction, Stack Overflow, Stack Underflow, MCLR, WWDT, (PWRT, OST) | |
| Instruction Set | 75
Instructions; 83 with Extended Instruction Set enabled | |
| Operating Frequency | DC – 64 MHz | |
| Note 1: RE3 is an input only pin. | ||
