3.1 Other TMR1 Features

Table 3-2. Features comparison between TMR1 and UTMR
Feature	TMR1	UTMR
Active Clock Edge	TMR1 increments at every rising edge of clock. In some cases, a falling edge must be registered before the timer starts incrementing.	Set CPOL = Rising Clock Edge to increment UTMR at rising clock edges.
Synchronization	TMR1 can operate either synchronous or asynchronous to the system clock based on SYNC bit setting.	UTMR always operates asynchronous to the system clock. The CSYNC bit is used to synchronize signals and commands going in and out of the UTMR module.
Buffered Read/Write	RD16 bit can be used to read/write 16-bits of TMRxH:L register in one atomic operation.	The TUxyTMR timer/counter register is not guarded for atomic access. However, the TUxyPR period register is double-buffered. Refer to section 1.1 UTMR Size and Buffered Access for details on UTMR buffered access to registers.
Prescaler	TMR1 has 4 programmable input prescaler options ranging from 1:1 to 1:8, which can be selected using CKPS bits.	UTMR has 256 programmable clock prescaler options ranging from 1:1 to 1:256, which can be selected using TUxyPS register.
Gate Source and Polarity	The gate source is selected using GSS bits and the polarity of the gate source is selected using GPOL bit.	The ERS signal acts as the gate source and can be selected using TUxyERS register. The ERS polarity can be selected using EPOL bit.
Gate Value Status	The most current value of gate level can be read using GVAL bit.	Use OM = Level output to represent the current run/stop state of UTMR, i.e. when the gate is activated and when it is not active. This is also represented using the RUN status bit.
Output	TMR1 output pulses every roll-over for one instruction clock.	Set TUxyPR to the maximum value and set OM = Pulse Output mode. This will cause a pulse for one timer clock period when the timer rolls over.
Interrupts	The TMRxGIF gate event interrupt occurs at the completion of a gate event. The TMRxIF timer interrupt occurs when the counter rolls-over to zero.	CIF capture interrupt can be used to signify completion of a gate event. ZIF zero interrupt can be used to signify a counter roll-over.
Sleep Mode Operation	TMR1 halts when operating synchronously. In asynchronous mode, TMR1 continues operating as long as the clock is active, and wakes up the CPU if interrupts are enabled.	UTMR continues to operate as long as the clock is active, and wakes up the CPU if interrupts are enabled.

Active Clock Edge

TMR1 increments at every rising edge of clock. In some cases, a falling edge must be registered before the timer starts incrementing.

Set CPOL = Rising Clock Edge to increment UTMR at rising clock edges.

Synchronization

TMR1 can operate either synchronous or asynchronous to the system clock based on SYNC bit setting.

UTMR always operates asynchronous to the system clock. The CSYNC bit is used to synchronize signals and commands going in and out of the UTMR module.

Buffered Read/Write

RD16 bit can be used to read/write 16-bits of TMRxH:L register in one atomic operation.

The TUxyTMR timer/counter register is not guarded for atomic access. However, the TUxyPR period register is double-buffered. Refer to section 1.1 UTMR Size and Buffered Access for details on UTMR buffered access to registers.

Prescaler

TMR1 has 4 programmable input prescaler options ranging from 1:1 to 1:8, which can be selected using CKPS bits.

UTMR has 256 programmable clock prescaler options ranging from 1:1 to 1:256, which can be selected using TUxyPS register.

Gate Source and Polarity

The gate source is selected using GSS bits and the polarity of the gate source is selected using GPOL bit.

The ERS signal acts as the gate source and can be selected using TUxyERS register. The ERS polarity can be selected using EPOL bit.

Gate Value Status

The most current value of gate level can be read using GVAL bit.

Use OM = Level output to represent the current run/stop state of UTMR, i.e. when the gate is activated and when it is not active. This is also represented using the RUN status bit.

Output

TMR1 output pulses every roll-over for one instruction clock.

Set TUxyPR to the maximum value and set OM = Pulse Output mode. This will cause a pulse for one timer clock period when the timer rolls over.

Interrupts

The TMRxGIF gate event interrupt occurs at the completion of a gate event. The TMRxIF timer interrupt occurs when the counter rolls-over to zero.

CIF capture interrupt can be used to signify completion of a gate event. ZIF zero interrupt can be used to signify a counter roll-over.

Sleep Mode Operation

TMR1 halts when operating synchronously. In asynchronous mode, TMR1 continues operating as long as the clock is active, and wakes up the CPU if interrupts are enabled.

UTMR continues to operate as long as the clock is active, and wakes up the CPU if interrupts are enabled.

TB3283

3.1 Other TMR1 Features