27.2 Overview

The USB peripheral is a USB 2.0 full-speed (12 Mbps) device-compliant interface.

16 endpoint addresses are supported, each with one input and one output endpoint, giving totally 32 configurable endpoints, including one control endpoint. Each endpoint address is supported by the four transfer types - Control, interrupt, bulk, or isochronous. The data payload size is also selectable. It supports data payloads up to 1023 bytes.

No dedicated memory is allocated for or included in the USB peripheral. The device’s internal SRAM keeps the configuration and the data buffer for each endpoint address. The memory locations used for endpoint configurations and data buffers are fully configurable. The amount of allocated memory is dynamic according to the configured number of endpoint addresses and the configuration of the endpoints. The USB peripheral has built-in direct memory access (DMA) and will read/write data from/to theSRAM during a USB transaction.

The multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint transferred as multiple packets without software intervention, reducing the CPU intervention and the interrupts needed for USB transfers.

For low-power operation, the microcontroller can enter any sleep mode except power down when the USB bus is idle and a suspend condition is given. Upon a bus resume, the USB peripheral can wake up the microcontroller.

The figures below provide overviews of how the USB peripheral performs USB OUT and IN transfers.