27.4 Register Summary - USBn


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	7:0	ENABLE		FIFOEN	STFRNUM	MAXEP[3:0]
0x01	CTRLB	7:0					URESUME	GNAUTO	GNAK	ATTACH
0x02	BUSSTATE	7:0				WTRSM	URESUME	DRESUME	SUSPENDED	BUSRST
0x03	ADDR	7:0		ADDR[6:0]
0x04	FIFOWP	7:0				FIFOWP[4:0]
0x05	FIFORP	7:0				FIFORP[4:0]
0x06	EPPTR	7:0	EPPTR[7:0]
0x06	EPPTR	15:8	EPPTR[15:8]
0x07	INTCTRLA	7:0	SOF	SUSPEND	RESUME	RESET	STALLED	UNF	OVF
0x08	INTCTRLB	7:0			TRNCOMPL				GNDONE	SETUP
0x09	INTFLAGSA	7:0	SOF	SUSPEND	RESUME	RESET	STALLED	UNF	OVF
0x0A	INTFLAGSB	7:0			TRNCOMPL			RMWBUSY	GNDONE	SETUP
0x0B ... 0x3F	Reserved
0x40	STATUS[0].OUTCLR	7:0	RMWSTATUS[7:0]
0x41	STATUS[0].OUTSET	7:0	RMWSTATUS[7:0]
0x42	STATUS[0].INCLR	7:0	RMWSTATUS[7:0]
0x43	STATUS[0].INSET	7:0	RMWSTATUS[7:0]
0x44	STATUS[1].OUTCLR	7:0	RMWSTATUS[7:0]
0x45	STATUS[1].OUTSET	7:0	RMWSTATUS[7:0]
0x46	STATUS[1].INCLR	7:0	RMWSTATUS[7:0]
0x47	STATUS[1].INSET	7:0	RMWSTATUS[7:0]
0x48	STATUS[2].OUTCLR	7:0	RMWSTATUS[7:0]
0x49	STATUS[2].OUTSET	7:0	RMWSTATUS[7:0]
0x4A	STATUS[2].INCLR	7:0	RMWSTATUS[7:0]
0x4B	STATUS[2].INSET	7:0	RMWSTATUS[7:0]
0x4C	STATUS[3].OUTCLR	7:0	RMWSTATUS[7:0]
0x4D	STATUS[3].OUTSET	7:0	RMWSTATUS[7:0]
0x4E	STATUS[3].INCLR	7:0	RMWSTATUS[7:0]
0x4F	STATUS[3].INSET	7:0	RMWSTATUS[7:0]
0x50	STATUS[4].OUTCLR	7:0	RMWSTATUS[7:0]
0x51	STATUS[4].OUTSET	7:0	RMWSTATUS[7:0]
0x52	STATUS[4].INCLR	7:0	RMWSTATUS[7:0]
0x53	STATUS[4].INSET	7:0	RMWSTATUS[7:0]
0x54	STATUS[5].OUTCLR	7:0	RMWSTATUS[7:0]
0x55	STATUS[5].OUTSET	7:0	RMWSTATUS[7:0]
0x56	STATUS[5].INCLR	7:0	RMWSTATUS[7:0]
0x57	STATUS[5].INSET	7:0	RMWSTATUS[7:0]
0x58	STATUS[6].OUTCLR	7:0	RMWSTATUS[7:0]
0x59	STATUS[6].OUTSET	7:0	RMWSTATUS[7:0]
0x5A	STATUS[6].INCLR	7:0	RMWSTATUS[7:0]
0x5B	STATUS[6].INSET	7:0	RMWSTATUS[7:0]
0x5C	STATUS[7].OUTCLR	7:0	RMWSTATUS[7:0]
0x5D	STATUS[7].OUTSET	7:0	RMWSTATUS[7:0]
0x5E	STATUS[7].INCLR	7:0	RMWSTATUS[7:0]
0x5F	STATUS[7].INSET	7:0	RMWSTATUS[7:0]
0x60	STATUS[8].OUTCLR	7:0	RMWSTATUS[7:0]
0x61	STATUS[8].OUTSET	7:0	RMWSTATUS[7:0]
0x62	STATUS[8].INCLR	7:0	RMWSTATUS[7:0]
0x63	STATUS[8].INSET	7:0	RMWSTATUS[7:0]
0x64	STATUS[9].OUTCLR	7:0	RMWSTATUS[7:0]
0x65	STATUS[9].OUTSET	7:0	RMWSTATUS[7:0]
0x66	STATUS[9].INCLR	7:0	RMWSTATUS[7:0]
0x67	STATUS[9].INSET	7:0	RMWSTATUS[7:0]
0x68	STATUS[10].OUTCLR	7:0	RMWSTATUS[7:0]
0x69	STATUS[10].OUTSET	7:0	RMWSTATUS[7:0]
0x6A	STATUS[10].INCLR	7:0	RMWSTATUS[7:0]
0x6B	STATUS[10].INSET	7:0	RMWSTATUS[7:0]
0x6C	STATUS[11].OUTCLR	7:0	RMWSTATUS[7:0]
0x6D	STATUS[11].OUTSET	7:0	RMWSTATUS[7:0]
0x6E	STATUS[11].INCLR	7:0	RMWSTATUS[7:0]
0x6F	STATUS[11].INSET	7:0	RMWSTATUS[7:0]
0x70	STATUS[12].OUTCLR	7:0	RMWSTATUS[7:0]
0x71	STATUS[12].OUTSET	7:0	RMWSTATUS[7:0]
0x72	STATUS[12].INCLR	7:0	RMWSTATUS[7:0]
0x73	STATUS[12].INSET	7:0	RMWSTATUS[7:0]
0x74	STATUS[13].OUTCLR	7:0	RMWSTATUS[7:0]
0x75	STATUS[13].OUTSET	7:0	RMWSTATUS[7:0]
0x76	STATUS[13].INCLR	7:0	RMWSTATUS[7:0]
0x77	STATUS[13].INSET	7:0	RMWSTATUS[7:0]
0x78	STATUS[14].OUTCLR	7:0	RMWSTATUS[7:0]
0x79	STATUS[14].OUTSET	7:0	RMWSTATUS[7:0]
0x7A	STATUS[14].INCLR	7:0	RMWSTATUS[7:0]
0x7B	STATUS[14].INSET	7:0	RMWSTATUS[7:0]
0x7C	STATUS[15].OUTCLR	7:0	RMWSTATUS[7:0]
0x7D	STATUS[15].OUTSET	7:0	RMWSTATUS[7:0]
0x7E	STATUS[15].INCLR	7:0	RMWSTATUS[7:0]
0x7F	STATUS[15].INSET	7:0	RMWSTATUS[7:0]