3.7 Source Code Overview

The key peripherals and parameters used in the source code are:

  • Main clock (CPU, peripherals) frequency: 10 MHz
  • Peripherals
    • RTC
      • RTC clock frequency: 1.024 kHz
      • PIT period: 512 cycles (0.5 seconds)
    • SLPCTRL
      • Sleep mode: Power-Down
    • DAC
      • Voltage reference: VDD (3.3V by default on CNANO board)
      • Output voltage: 1.8V
    • ADC
      • Clock frequency: 5 MHz (main clock divided by 2)
      • Voltage reference: VREFA
      • Sample accumulation: 16
      • PGA gain: 16x
      • PGA bias current: 100%
  • Interrupts
    • RTC PIT Interrupt (RTC_PIT_vect)

The following figure shows the high-level flow of the code:

Figure 3-1. High-level flow of voltage sensing code