18.5.16 Pin n Control


Bit	7	6	5	4	3	2	1	0
	INVEN	INLVL			PULLUPEN	ISC[2:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 7 – INVEN Inverted I/O Enable

This bit controls whether the input and output for pin n are inverted or not.

Value	Description
0	Input and output values are not inverted
1	Input and output values are inverted

Bit 6 – INLVL Input Level Select

This bit controls the input voltage threshold for pin n, used for port input reads and interrupt conditions.

Value	Name	Description
0	ST	Schmitt Trigger derived from supply level
1	TTL	TTL Levels

Bit 3 – PULLUPEN Pull-Up Enable

This bit controls whether the internal pull-up of pin n is enabled or not when the pin is configured as input-only.

Value	Description
0	Pull-up disabled
1	Pull-up enabled

Bits 2:0 – ISC[2:0] Input/Sense Configuration

This bit field controls the input and sense configuration of pin n. The sense configuration determines the pin conditions that will trigger a port interrupt.

Note:

If the digital input buffer for pin n is disabled, bit n in the Input Value (PORTx.IN) register will not be updated.
The LEVEL interrupt will keep triggering continuously as long as the pin stays low.

Value	Name	Description
0x0	INTDISABLE	Interrupt disabled but digital input buffer enabled
0x1	BOTHEDGES	Interrupt enabled with sense on both edges
0x2	RISING	Interrupt enabled with sense on rising edge
0x3	FALLING	Interrupt enabled with sense on falling edge
0x4	INPUT_DISABLE	Interrupt and digital input buffer disabled⁽¹⁾
0x5	LEVEL	Interrupt enabled with sense on low level⁽²⁾
other	—	Reserved

Name:	PINnCTRL
Offset:	0x10 + n*0x01 [n=0..7]
Reset:	0x00
Property:	-