28.5.3 Interrupt Control
| Name: | INTCTRL |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RXCIE | TXCIE | DREIE | SSIE | IE | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – RXCIE Receive Complete Interrupt Enable
In Buffer mode, this bit enables the Receive Complete interrupt. The
enabled interrupt will be triggered when the RXCIF in the SPIn.INTFLAGS register
is set. In the Non-Buffer mode, this bit is ‘0’.
Bit 6 – TXCIE Transfer Complete Interrupt Enable
In Buffer mode, this bit enables the Transfer Complete interrupt.
The enabled interrupt will be triggered when the TXCIF in the SPIn.INTFLAGS
register is set. In the Non-Buffer mode, this bit is ‘0’.
Bit 5 – DREIE Data Register Empty Interrupt Enable
In Buffer mode, this bit enables the Data Register Empty interrupt.
The enabled interrupt will be triggered when the DREIF in the SPIn.INTFLAGS
register is set. In the Non-Buffer mode, this bit is ‘0’.
Bit 4 – SSIE Client Select Trigger Interrupt Enable
In Buffer mode, this bit enables the Client Select interrupt. The enabled
interrupt will be triggered when the SSIF in the SPIn.INTFLAGS register is set.
In the Non-Buffer mode, this bit is ‘0’.
Bit 0 – IE Interrupt Enable
This bit enables the SPI interrupt when the SPI is not in Buffer mode. The enabled interrupt will be triggered when RXCIF/IF is set in the SPIn.INTFLAGS register.