28.5.2 Control B
| Name: | CTRLB |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BUFEN | BUFWR | SSD | MODE[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 7 – BUFEN Buffer Mode Enable
1’ enables Buffer mode. This will enable two receive buffers
and one transmit buffer. Both will have separate interrupt flags, transmit complete
and receive complete.Bit 6 – BUFWR Buffer Mode Wait for Receive
When writing this bit to ‘0’, the first data transferred will be
a dummy sample.
| Value | Description |
|---|---|
| 0 | One SPI transfer must be completed before the data are copied into the shift register |
| 1 | If writing to the Data register when the SPI is enabled and SS is high, the first write will go directly to the shift register |
Bit 2 – SSD Client Select Disable
If this bit is set when operating as SPI Host (MASTER = 1 in
SPIn.CTRLA), SS does not disable Host mode.
| Value | Description |
|---|---|
| 0 | Enable the Client Select line when operating as SPI host |
| 1 | Disable the Client Select line when operating as SPI host |
Bits 1:0 – MODE[1:0] Mode
These bits select the Transfer mode. The four combinations of SCK phase and polarity concerning the serial data are shown below. These bits decide whether the first edge of a clock cycle (leading edge) is rising or falling and whether data setup and sample occur on the leading or trailing edge. When the leading edge is rising, the SCK signal is low when Idle, and when the leading edge is falling, the SCK signal is high when Idle.
| Value | Name | Description |
|---|---|---|
| 0x0 | 0 |
Leading edge: Rising, sample |
| 0x1 | 1 |
Leading edge: Rising, setup |
| 0x2 | 2 |
Leading edge: Falling, sample |
| 0x3 | 3 |
Leading edge: Falling, setup |