23.3.4.6 High Resolution

The high resolution can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, Single-Slope PWM, or Dual-Slope PWM generation. It can also be used with the WEX if used for the same timer/counter.

The high-resolution extension uses a clock source of 4x: In 4x mode, the rising edges are counted, and to obtain 8x, both edges are counted.

Figure 23-13. Timer/Counter with High-Resolution Extension

When the high-resolution extension is enabled, the timer/counter must run from a non-prescaled peripheral clock.

For full utilization of high-resolution, a clock running at 4x the desired CPU speed must be available. If the desired system speed is 20 MHz, then Phase Locked Loop (PLL) must be enabled for the system (PLL must be selected in MCLKCTRL.CLKSEL to obtain an 80 MHz source) and enable PRESCB (MCLKCTRL.PBDIV). This results in an 80 MHz source for high-resolution and 20 MHz for the system clock/peripheral clock.

The Timer/Counter will ignore its least significant bits (LSb) in the counter, according to selection in the High Resolution Enable (HREN[1:0]) bit field in the Control D (TCEn.CTRLD) register. Overflow/underflow and compare match of the most significant bits (MSb) is done in the timer/counter. Count and compare the LSb is handled and compared in the hi-res extension running from the clock operating at 4x or 8x the system clock.

Figure 23-14 shows that only one edge of the PWM is affected when high resolution is enabled, and it is the LSbs of the compare register that define the fraction of CLK_PER:

Figure 23-14. Duty Cycle Control

Since the LSbs are unused for the period, the PWM frequency will change when high resolution is enabled. See Table 23-4.

Table 23-4. High-Resolution Influence on Counter and Waveform
HREN	LSbs used for Hi-Res	Counter inc/dec	f_FRQ	f_SS	f_DS
OFF	0	±1	$\frac{f_{C L K_P E R}}{2 N (C M P 0 + 1)}$	$\frac{f_{C L K_P E R}}{N (P E R + 1)}$	$\frac{f_{C L K_P E R}}{2 N (P E R)}$
4X	2	±4	$\frac{{4 f}_{C L K_P E R}}{2 N (C M P 0 + 4)}$	$\frac{{4 f}_{C L K_P E R}}{N (P E R + 4)}$	$\frac{{4 f}_{C L K_P E R}}{2 N (P E R)}$
8X	3	±8	$\frac{{8 f}_{C L K_P E R}}{2 N (C M P 0 + 8)}$	$\frac{{8 f}_{C L K_P E R}}{N (P E R + 8)}$	$\frac{{8 f}_{C L K_P E R}}{2 N (P E R)}$

The LSbs of the timer/counter period register must be set to zero to ensure correct operation. If the count register is read from the application code, the LSb will always be read as zero since the timer/counter runs from the peripheral clock. The LSbs are also ignored when generating events.

The TCE in High Resolution mode will not output any pulse shorter than one peripheral clock cycle; i.e., a compare value lower than four will have no visible output.