18.7.1 Data Direction
| Name: | DIR |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | - |
Access to the Virtual PORT registers has the same outcome as access to the regular registers allowing for memory-specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space where the regular PORT registers reside.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – DIR[7:0] Data Direction
This bit field does not control the digital input buffer. The digital input buffer for pin n (Pxn) can be configured in the Input/Sense Configuration (ISC) bit field in the Pin n Control (PORTx.PINnCTRL) register.
The table below shows the available configuration for each bit n in this bit field.
| Value | Description |
|---|---|
| 0 | Pxn is configured as an input-only pin, and the output driver is disabled |
| 1 | Pxn is configured as an output pin, and the output driver is enabled |