18.7.2 Output Value
| Name: | OUT |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
Access to the Virtual PORT registers has the same outcome as access to the regular registers allowing for memory-specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space where the regular PORT registers reside.
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OUT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – OUT[7:0] Output Value
This configuration only affects the output when the output driver (PORTx.DIR) is enabled for the corresponding pin.
The table below shows the available configuration for each bit n in this bit field.
| Value | Description |
|---|---|
| 0 | The pin n (Pxn) output is driven low |
| 1 | The Pxn output is driven high |