4.1 Revision History


Doc. Rev.	Date	Comments
E	05/2024	Document: Editorial updates Added new errata: Device: 2.2.2 Writing the OSCLOCK Fuse in FUSE.OSCCFG to ‘`1`’ Prevents Automatic Loading of Calibration Values NVMCTRL: 2.5.1 Wrong Reset Value of NVMCTRL.CTRLA Register USART: 2.8.3 Receiver Non-Functional after Detection of Inconsistent Synchronization Field Added new data sheet clarifications: I/O Multiplexing and Considerations: 3.1.1 I/O Multiplexing Electrical Characteristics: 3.2.1 I/O Pin Characteristics 3.2.2 SPI - Timing Characteristics 3.2.3 Programming Time
D	01/2022	Added erratum: ADC: 2.3.1 ADC Stays Active in Sleep Modes for Low Latency Mode and Free Running Mode Updated erratum: Device: 2.2.1 IDD Power-Down Current Consumption Updated data sheet clarification: Removed Fuses - Correct Factory Default Value for Reserved Fuse Bits is ‘`1`’
C	06/2021	Updated errata: Device: 2.2.1 IDD Power-Down Current Consumption USART: 2.8.2 Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode
B	12/2020	Silicon revision D not released to production. Silicon revision E is the initial release: Removed silicon revision D from Silicon Issues Summary and all Affected Versions tables Removed all errata only applicable to silicon revision D Added errata: Device: IDD Power-Down Current Consumption CCL: The CCL Must be Disabled to Change the Configuration of a Single LUT TCA: Restart Will Reset Counter Direction in NORMAL and FRQ Mode TCB: CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode USART: Open-Drain Mode Does Not Work When TXD is Configured as Output Added data sheet clarification: Fuses: Correct Factory Default Value for Reserved Fuse Bits is ‘`1`’
A	07/2020	Initial document release