16.15 Register Summary - I/O Ports
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x0B | Reserved | |||||||||
| 0x0C | PORTA | 7:0 | RA7 | RA6 | RA5 | RA4 | RA3 | RA2 | RA1 | RA0 |
| 0x0D | PORTB | 7:0 | RB7 | RB6 | RB5 | RB4 | RB3 | RB2 | RB1 | RB0 |
| 0x0E | PORTC | 7:0 | RC7 | RC6 | RC5 | RC4 | RC3 | RC2 | RC1 | RC0 |
| 0x0F | PORTD | 7:0 | RD7 | RD6 | RD5 | RD4 | RD3 | RD2 | RD1 | RD0 |
| 0x10 | PORTE | 7:0 | RE3 | RE2 | RE1 | RE0 | ||||
0x11 | Reserved | |||||||||
| 0x12 | TRISA | 7:0 | TRISA7 | TRISA6 | TRISA5 | TRISA4 | TRISA3 | TRISA2 | TRISA1 | TRISA0 |
| 0x13 | TRISB | 7:0 | TRISB7 | TRISB6 | TRISB5 | TRISB4 | TRISB3 | TRISB2 | TRISB1 | TRISB0 |
| 0x14 | TRISC | 7:0 | TRISC7 | TRISC6 | TRISC5 | TRISC4 | TRISC3 | TRISC2 | TRISC1 | TRISC0 |
| 0x15 | TRISD | 7:0 | TRISD7 | TRISD6 | TRISD5 | TRISD4 | TRISD3 | TRISD2 | TRISD1 | TRISD0 |
| 0x16 | TRISE | 7:0 | Reserved | TRISE2 | TRISE1 | TRISE0 | ||||
0x17 | Reserved | |||||||||
| 0x18 | LATA | 7:0 | LATA7 | LATA6 | LATA5 | LATA4 | LATA3 | LATA2 | LATA1 | LATA0 |
| 0x19 | LATB | 7:0 | LATB7 | LATB6 | LATB5 | LATB4 | LATB3 | LATB2 | LATB1 | LATB0 |
| 0x1A | LATC | 7:0 | LATC7 | LATC6 | LATC5 | LATC4 | LATC3 | LATC2 | LATC1 | LATC0 |
| 0x1B | LATD | 7:0 | LATD7 | LATD6 | LATD5 | LATD4 | LATD3 | LATD2 | LATD1 | LATD0 |
| 0x1C | LATE | 7:0 | LATE2 | LATE1 | LATE0 | |||||
0x1D ... 0x1E8B | Reserved | |||||||||
| 0x1E8C | ANSELA | 7:0 | ANSELA7 | ANSELA6 | ANSELA5 | ANSELA4 | ANSELA3 | ANSELA2 | ANSELA1 | ANSELA0 |
| 0x1E8D | WPUA | 7:0 | WPUA7 | WPUA6 | WPUA5 | WPUA4 | WPUA3 | WPUA2 | WPUA1 | WPUA0 |
| 0x1E8E | ODCONA | 7:0 | ODCA7 | ODCA6 | ODCA5 | ODCA4 | ODCA3 | ODCA2 | ODCA1 | ODCA0 |
| 0x1E8F | SLRCONA | 7:0 | SLRA7 | SLRA6 | SLRA5 | SLRA4 | SLRA3 | SLRA2 | SLRA1 | SLRA0 |
| 0x1E90 | INLVLA | 7:0 | INLVLA7 | INLVLA6 | INLVLA5 | INLVLA4 | INLVLA3 | INLVLA2 | INLVLA1 | INLVLA0 |
0x1E91 ... 0x1E95 | Reserved | |||||||||
| 0x1E96 | ANSELB | 7:0 | ANSELB7 | ANSELB6 | ANSELB5 | ANSELB4 | ANSELB3 | ANSELB2 | ANSELB1 | ANSELB0 |
| 0x1E97 | WPUB | 7:0 | WPUB7 | WPUB6 | WPUB5 | WPUB4 | WPUB3 | WPUB2 | WPUB1 | WPUB0 |
| 0x1E98 | ODCONB | 7:0 | ODCB7 | ODCB6 | ODCB5 | ODCB4 | ODCB3 | ODCB2 | ODCB1 | ODCB0 |
| 0x1E99 | SLRCONB | 7:0 | SLRB7 | SLRB6 | SLRB5 | SLRB4 | SLRB3 | SLRB2 | SLRB1 | SLRB0 |
| 0x1E9A | INLVLB | 7:0 | INLVLB7 | INLVLB6 | INLVLB5 | INLVLB4 | INLVLB3 | INLVLB2 | INLVLB1 | INLVLB0 |
0x1E9B ... 0x1E9F | Reserved | |||||||||
| 0x1EA0 | ANSELC | 7:0 | ANSELC7 | ANSELC6 | ANSELC5 | ANSELC4 | ANSELC3 | ANSELC2 | ANSELC1 | ANSELC0 |
| 0x1EA1 | WPUC | 7:0 | WPUC7 | WPUC6 | WPUC5 | WPUC4 | WPUC3 | WPUC2 | WPUC1 | WPUC0 |
| 0x1EA2 | ODCONC | 7:0 | ODCC7 | ODCC6 | ODCC5 | ODCC4 | ODCC3 | ODCC2 | ODCC1 | ODCC0 |
| 0x1EA3 | SLRCONC | 7:0 | SLRC7 | SLRC6 | SLRC5 | SLRC4 | SLRC3 | SLRC2 | SLRC1 | SLRC0 |
| 0x1EA4 | INLVLC | 7:0 | INLVLC7 | INLVLC6 | INLVLC5 | INLVLC4 | INLVLC3 | INLVLC2 | INLVLC1 | INLVLC0 |
0x1EA5 ... 0x1EA9 | Reserved | |||||||||
| 0x1EAA | ANSELD | 7:0 | ANSELD7 | ANSELD6 | ANSELD5 | ANSELD4 | ANSELD3 | ANSELD2 | ANSELD1 | ANSELD0 |
| 0x1EAB | WPUD | 7:0 | WPUD7 | WPUD6 | WPUD5 | WPUD4 | WPUD3 | WPUD2 | WPUD1 | WPUD0 |
| 0x1EAC | ODCOND | 7:0 | ODCD7 | ODCD6 | ODCD5 | ODCD4 | ODCD3 | ODCD2 | ODCD1 | ODCD0 |
| 0x1EAD | SLRCOND | 7:0 | SLRD7 | SLRD6 | SLRD5 | SLRD4 | SLRD3 | SLRD2 | SLRD1 | SLRD0 |
| 0x1EAE | INLVLD | 7:0 | INLVLD7 | INLVLD6 | INLVLD5 | INLVLD4 | INLVLD3 | INLVLD2 | INLVLD1 | INLVLD0 |
0x1EAF ... 0x1EB3 | Reserved | |||||||||
| 0x1EB4 | ANSELE | 7:0 | ANSELE2 | ANSELE1 | ANSELE0 | |||||
| 0x1EB5 | WPUE | 7:0 | WPUE3 | WPUE2 | WPUE1 | WPUE0 | ||||
| 0x1EB6 | ODCONE | 7:0 | ODCE2 | ODCE1 | ODCE0 | |||||
| 0x1EB7 | SLRCONE | 7:0 | SLRE2 | SLRE1 | SLRE0 | |||||
| 0x1EB8 | INLVLE | 7:0 | INLVLE3 | INLVLE2 | INLVLE1 | INLVLE0 | ||||
0x1EB9 ... 0x1EE2 | Reserved | |||||||||
| 0x1EE3 | RB1I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x1EE4 | RB2I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
0x1EE5 ... 0x1EEA | Reserved | |||||||||
| 0x1EEB | RC3I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x1EEC | RC4I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
0x1EED | Reserved | |||||||||
| 0x1EEE | RD0I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||
| 0x1EEF | RD1I2C | 7:0 | SLEW | PU[1:0] | TH[1:0] | |||||