18.2 PPS Inputs
Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the table below).
Important: The notation “xxx” in the generic register name
is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS
register.
Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.
| Peripheral | PPS Input Register | Default Pin Selection at POR | Register Reset Value at POR | Available Input Port | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 28-Pin Devices | 40-Pin Devices | ||||||||||
| External Interrupt | INTPPS | RB0 | ‘b001 000 |
A | B | — | A | B | — | — | — |
| Timer0 Clock | T0CKIPPS | RA4 | ‘b000 100 |
A | B | — | A | B | — | — | — |
| Timer1 Clock | T1CKIPPS | RC0 | ‘b010 000 |
A | — | C | A | — | C | — | — |
| Timer1 Gate | T1GPPS | RB5 | ‘b001 101 |
— | B | C | — | B | C | — | — |
| Timer3 Clock | T3CKIPPS | RC0 | ‘b010 000 |
— | B | C | — | B | C | — | — |
| Timer3 Gate | T3GPPS | RC0 | ‘b010 000 |
A | — | C | A | — | C | — | — |
| Timer2 Input | T2INPPS | RC3 | ‘b010 011 |
A | — | C | A | — | C | — | — |
| Timer4 Input | T4INPPS | RC5 | ‘b010 101 |
— | B | C | — | B | C | — | — |
| Timer6 Input | T6INPPS | RB7 | ‘b001 111 |
— | B | C | — | B | — | D | — |
| CCP1 | CCP1PPS | RC2 | ‘b010 010 |
— | B | C | — | B | C | — | — |
| CCP2 | CCP2PPS | RC1 | ‘b010 001 |
— | B | C | — | B | C | — | — |
| PWM Input 0 | PWMIN0PPS | RC2 | ‘b010 010 |
— | B | C | — | B | C | — | — |
| PWM Input 1 | PWMIN1PPS | RC1 | ‘b010 001 |
— | B | C | — | B | C | — | — |
| PWM1 External Reset | PWMIN1ERSPPS | RC3 | ‘b010 011 |
A | — | C | A | — | C | — | — |
| PWM2 External Reset | PWMIN2ERSPPS | RC5 | ‘b010 101 |
— | B | C | — | B | C | — | — |
| PWM3 External Reset | PWMIN3ERSPPS | RB7 | ‘b001 111 |
— | B | C | — | B | C | — | — |
| PWM4 External Reset | PWMIN4ERSPPS | RC3 | ‘b010 011 |
A | — | C | A | — | C | — | — |
| CWG1 | CWG1PPS | RB0 | ‘b001 000 |
— | B | C | — | B | — | D | — |
| CLCIN0 | CLCIN0PPS | RA0 | ‘b000 000 |
A | — | C | A | — | C | — | — |
| CLCIN1 | CLCIN1PPS | RA1 | ‘b000 001 |
A | — | C | A | — | C | — | — |
| CLCIN2 | CLCIN2PPS | RB6 | ‘b001 110 |
— | B | C | — | B | — | D | — |
| CLCIN3 | CLCIN3PPS | RB7 | ‘b001 111 |
— | B | C | — | B | — | D | — |
| SCL1/SCK1 | SSP1CLKPPS(1) | RC3 | ‘b010 011 |
— | B | C | — | B | C | — | — |
| SDA1/SDI1 | SSP1DATPPS(1) | RC4 | ‘b010 100 |
— | B | C | — | B | C | — | — |
| SS1 | SSP1SSPPS | RA5 | ‘b000 101 |
A | — | C | A | — | — | D | — |
| SCL2/SCK2 | SSP2CLKPPS(1) | RB1 | ‘b001 001 |
— | B | C | — | B | — | D | — |
| SDA2/SDI2 | SSP2DATPPS(1) | RB2 | ‘b001 010 |
— | B | C | — | B | — | D | — |
| SS2 | SSP2SSPPS | RB0 | ‘b001 000 |
— | B | C | — | B | — | D | — |
| RX1/DT1 | RX1PPS | RC7 | ‘b010 111 |
— | B | C | — | B | C | — | — |
| CK1 | CK1PPS | RC6 | ‘b010 110 |
— | B | C | — | B | C | — | — |
| RX2/DT2 | RX2PPS | RB7 | ‘b001 111 |
— | B | C | — | B | — | D | — |
| CK2 | CK2PPS | RB6 | ‘b001 110 |
— | B | C | — | B | — | D | — |
| ADC Conversion Trigger | ADACTPPS | RB4 | ‘b001 100 |
— | B | C | — | B | — | D | — |
| OPA1 Input | OPA1PPS | RA0 | ‘b000 000 |
A | — | C | A | — | C | — | — |
Note:
- Bidirectional pin. The corresponding output must select the same pin.