41.2 Standard Instruction Set

Table 41-3. Instruction Set
Mnemonic, Operands		Description	Cycles	14-Bit Opcode				Status Affected	Notes
Mnemonic, Operands		Description	Cycles	MSb			LSb	Status Affected	Notes
BYTE-ORIENTED OPERATIONS
ADDWF	f, d	Add WREG and f	1	`00`	`0111`	`dfff`	`ffff`	C, DC, Z	2
ADDWFC	f, d	Add WREG and Carry bit to f	1	`11`	`1101`	`dfff`	`ffff`	C, DC, Z	2
ANDWF	f, d	AND WREG with f	1	`00`	`0101`	`dfff`	`ffff`	Z	2
ASRF	f, d	Arithmetic Right Shift	1	`11`	`0111`	`dfff`	`ffff`	C, Z	2
LSLF	f, d	Logical Left Shift	1	`11`	`0101`	`dfff`	`ffff`	C, Z	2
LSRF	f, d	Logical Right Shift	1	`11`	`0110`	`dfff`	`ffff`	C, Z	2
CLRF	f	Clear f	1	`00`	`0001`	`lfff`	`ffff`	Z	2
CLRW	–	Clear WREG	1	`00`	`0001`	`0000`	`00xx`	Z
COMF	f, d	Complement f	1	`00`	`1001`	`dfff`	`ffff`	Z	2
DECF	f, d	Decrement f	1	`00`	`0011`	`dfff`	`ffff`	Z	2
INCF	f, d	Increment f	1	`00`	`1010`	`dfff`	`ffff`	Z	2
IORWF	f, d	Inclusive OR WREG with f	1	`00`	`0100`	`dfff`	`ffff`	Z	2
MOVF	f, d	Move f	1	`00`	`1000`	`dfff`	`ffff`	Z	2
MOVWF	f	Move WREG to f	1	`00`	`0000`	`1fff`	`ffff`	None	2
RLF	f, d	Rotate Left f through Carry	1	`00`	`1101`	`dfff`	`ffff`	C	2
RRF	f, d	Rotate Right f through Carry	1	`00`	`1100`	`dfff`	`ffff`	C	2
SUBWF	f, d	Subtract WREG from f	1	`00`	`0010`	`dfff`	`ffff`	C, DC, Z	2
SUBWFB	f, d	Subtract WREG from f with   Borrow	1	`11`	`1011`	`dfff`	`ffff`	C, DC, Z	2
SWAPF	f, d	Swap nibbles in f	1	`00`	`1110`	`dfff`	`ffff`	None	2
XORWF	f, d	Exclusive OR WREG with f	1	`00`	`0110`	`dfff`	`ffff`	Z	2
BYTE-ORIENTED SKIP OPERATIONS
DECFSZ	f, d	Decrement f, Skip if 0	1(2)	`00`	`1011`	`dfff`	`ffff`	None	1, 2
INCFSZ	f, d	Increment f, Skip if 0	1(2)	`00`	`1111`	`dfff`	`ffff`	None	1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF	f, b	Bit Clear f	1	`01`	`00bb`	`bfff`	`ffff`	None	2
BSF	f, b	Bit Set f	1	`01`	`01bb`	`bfff`	`ffff`	None	2
BIT-ORIENTED SKIP OPERATIONS
BTFSC	f, b	Bit Test f, Skip if Clear	1(2)	`01`	`10bb`	`bfff`	`ffff`	None	1, 2
BTFSS	f, b	Bit Test f, Skip if Set	1(2)	`1010`	`11bb`	`bfff`	`ffff`	None	1, 2
LITERAL OPERATIONS
ADDLW	k	Add literal and WREG	1	`11`	`1110`	`kkkk`	`kkkk`	C, DC, Z
ANDLW	k	AND literal with WREG	1	`11`	`1001`	`kkkk`	`kkkk`	Z
IORLW	k	Inclusive OR literal with WREG	1	`11`	`1000`	`kkkk`	`kkkk`	Z
MOVLB	k	Move literal to BSR	1	`00`	`000`	`0k`	`kkkk`	None
MOVLP	k	Move literal to PCLATH	1	`11`	`0001`	`1kkk`	`kkkk`	None
MOVLW	k	Move literal to W	1	`11`	`0000`	`kkkk`	`kkkk`	None
SUBLW	k	Subtract W from literal	1	`11`	`1100`	`kkkk`	`kkkk`	C, DC, Z
XORLW	k	Exclusive OR literal with W	1	`11`	`1010`	`kkkk`	`kkkk`	Z
CONTROL OPERATIONS
BRA	k	Relative Branch	2	`11`	`001k`	`kkkk`	`kkkk`	None
BRW	—	Relative Branch with WREG	2	`00`	`0000`	`0000`	`1011`	None
CALL	k	Call Subroutine	2	`10`	`0kkk`	`kkkk`	`kkkk`	None
CALLW	—	Call Subroutine with WREG	2	`00`	`0000`	`0000`	`1010`	None
GOTO	k	Go to address	2	`10`	`1kkk`	`kkkk`	`kkkk`	None
RETFIE	k	Return from interrupt	2	`00`	`0000`	`0000`	`1001`	None
RETLW	k	Return with literal in WREG	2	`11`	`0100`	`kkkk`	`kkkk`	None
RETURN	—	Return from Subroutine	2	`00`	`0000`	`0000`	`1000`	None
INHERENT OPERATIONS
CLRWDT	—	Clear Watchdog Timer	1	`00`	`0000`	`0110`	`0100`	TO, PD
NOP	—	No Operation	1	`00`	`0000`	`0000`	`0000`	None
RESET	—	Software device Reset	1	`00`	`0000`	`0000`	`0001`	None
SLEEP	—	Go into Standby mode	1	`00`	`0000`	`0110`	`0011`	TO, PD
TRIS	f	Load TRIS register with WREG	1	`00`	`0000`	`0110`	`0fff`	None
C-COMPILER OPTIMIZED
ADDFSR	n, k	Add Literal k to FSRn	1	`11`	`0001`	`0nkk`	`kkkk`	None
MOVIW	n, mm	Move Indirect FSRn to WREG with pre/post inc/dec modifier, mm	1	`00`	`0000`	`0001`	`0nmm`	Z	2, 3
MOVIW	k[n]	Move INDFn to WREG, Indexed Indirect.	1	`11`	`1111`	`0nkk`	`kkkk`	Z	2
MOVWI	n, mm	Move WREG to Indirect FSRn with pre/post inc/dec modifier, mm	1	`00`	`0000`	`0001`	`1nmm`	None	2, 3
MOVWI	k[n]	Move WREG to INDFn, Indexed Indirect.	1	`11`	`1111`	`1nkk`	`kkkk`	None	2

Note:

If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.
Details on MOVIW and MOVWI instruction descriptions are available in the next section.