1.6 Channel to Channel Crosstalk and Error

Another possible source of crosstalk is from another analog channel. This can be created by fast edges, like digital logic (see Crosstalk and PCB Routing), or an error can be transferred through the sample-and-hold capacitor (CSAMPLE) inside the ADC. The remaining charge on the sample-and-hold capacitor is transferred into the second channel if the ADC first samples a channel that charges the capacitor and then attempts to measure another channel. For a low-Z signal source on the second channel, the charge dissipates quickly. A high-Z signal source on the second channel will dissipate this charge at a much slower rate.

There are three ways to reduce this type of crosstalk:
  1. Buffer the high-Z channel to reduce the source impedance (see Buffering with an Operational Amplifier).
  2. Discharge the sample-and-hold capacitor before switching to the high-Z channel.
    • Do this by selecting the VSS/GND channel in the device or grounding an analog input pin and measuring that channel.
  3. Add an external capacitor to the high-Z channel.

The purpose of the external capacitor on the high-Z channel in suggestion c. is to provide a relatively large amount of reserve charge to minimize the change in voltage. The amount of charge on the capacitor is equal to:

Q =   C V

Where: Q is the stored charge (in Coulombs), C is capacitance, and V is voltage.

If a capacitor of size CEXT is connected to the high-Z channel, the change in voltage can be estimated based on the change in total capacitance. The worst-case change occurs when the CEXT is fully discharged, and CSAMPLE is fully charged.

V E R R O R ( M A X ) ⁢ = V R E F   * C S A M P L E C S A M P L E + C E X T

However, adding external capacitance to a channel causes two other changes of note. Firstly, the time constant significantly increases, which reduces the bandwidth of the channel. But, if CEXT is already charged and has a much larger capacitance than CSAMPLE, the acquisition time significantly reduces(1) if the capacitor voltage (after connecting CEXT and CSAMPLE) is within 0.5 LSbs of the input signal.

The worst-case for balancing charge occurs when CSAMPLE is fully discharged, and CEXT is fully charged. In this scenario, estimate the optimal external capacitance(2)(3) with the following formula:

C E X T ⁢ = C S A M P L E   ( 2 n + 1 − 1 )

Where: n = the number of bits in the result.

Note:
  1. Assuming the resistance of CEXT is negligible.
  2. For stability, select a capacitor dielectric with a low voltage coefficient, such as NP0 or C0G.
  3. Caution must be used when a large capacitor is on an I/O line. The ESD diodes will discharge the capacitor into the power rail, which may cause unusual issues with a device reset and potentially damage the device if the microcontroller powers off with this capacitor fully charged.