18.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register, with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports, with the exception of the following signals, which are routed to three ports:
  • CLBINxPPS
  • CLBCLKPPS
Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 18-1. PPS Input Selection Table
PeripheralPPS Input RegisterDefault Pin Selection at PORRegister Reset Value at PORAvailable Input Port
28-Pin Devices40-Pin Devices
External Interrupt INTPPSRB0‘b001 010AB—AB———
Timer0 ClockT0CKIPPSRA4‘b000 100AB—AB———
Timer1 ClockT1CKIPPSRC0‘b010 000A—CA—C——
Timer1 GateT1GPPSRB5‘b001 101—BC—BC——
Timer3 ClockT3CKIPPSRC0‘b010 000—BC—BC——
Timer3 GateT3GPPSRC0‘b010 000A—CA—C——
Timer2 InputT2INPPSRC3‘b010 011A—CA—C——
Timer4 InputT4INPPSRC5‘b010 101—BC—BC——
CCP1CCP1PPSRC2‘b010 010—BC—BC——
CCP2CCP2PPSRC1‘b010 001—BC—BC——
PWM Input 0PWMIN0PPSRC2‘b010 010—BC—BC——
PWM Input 1PWMIN1PPSRC1‘b010 001—BC—BC——
PWM1 External ResetPWMIN1ERSPPSRC3‘b010 011A—CA—C——
PWM2 External ResetPWMIN2ERSPPSRC5‘b010 101—BC—BC——
CLCIN0CLCIN0PPSRA0‘b000 000A—CA—C——
CLCIN1CLCIN1PPSRA1‘b000 001A—CA—C——
CLCIN2CLCIN2PPSRB6‘b001 110—BC—B—D—
CLCIN3CLCIN3PPSRB7‘b001 111—BC—B—D—
SCL1/SCK1SSP1CLKPPS(1)RC3‘b010 011—BC—BC——
SDA1/SDI1SSP1DATPPS(1)RC4‘b010 100—BC—BC——
SS1SSP1SSPPSRA5‘b000 101A—CA——D—
SCL2/SCK2SSP2CLKPPS(1)RB1‘b001 001—BC—B—C—
SDA2/SDI2SSP2DATPPS(1)RB2‘b001 010—BC—B—C—
SS2SSP2SSPPSRB0‘b001 000—BC—B—D—
RX1/DT1RX1PPSRC7‘b010 111—BC—BC——
CK1CK1PPSRC6‘b010 110—BC—BC——
RX2/DT2RX2PPSRB7‘b001 111—BC—B—D—
CK2CK2PPSRB6‘b001 110—BC—B—D—
ADC Conversion TriggerADACTPPSRB4‘b001 100—BC—B—D—
CLB ClockCLBCLKPPSRC4‘b001 100ABCABCDE
CLB Input 0CLBIN0PPSRC0‘b001 000ABCABCDE
CLB Input 1CLBIN1PPSRC1‘b001 001ABCABCDE
CLB Input 2CLBIN2PPSRC2‘b001 010ABCABCDE
CLB Input 3CLBIN3PPSRC3‘b001 011ABCABCDE
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.