3.7 Resolved Issues

(Ask a Question)

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2024.1 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 3-6. Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number	Summary	Resolution
01158513, 01320431	Hold violations in the PLL External FB logic for PF_CCC.	Exploring and finding more entries for inserting delay buffers to fix hold violations.
01282925, 01352373	Scramble enabled/disable option in transceiver configurator is not working properly for simulation.	The configurator user interface has been updated to account for missing design rule checks (DRCs).
1292044	PF_SOC: MSS: DDR: MemoryView: Support for DQ width 16 for DDR3 and LPDDR3.	PolarFire SoC MSS Configurator has been updated to support a DQ width of 16 for DDR3 and LPDDR3.
1096986	HDL_LANGUAGE: Libero/Synplify error CD150 on valid VHDL code.	This issue has been resolved by adding support to the valid VHDL code.
1094622	ModelSim v2022.2 is generating an error with the generic packages.	The generic package error has been resolved with the 2023.4 version of ModelSim ME Pro.
1134854	Libero synthesis configuration option values do not match those in the documentation.	Updated the PolarFire Design Flow User Guide to reflect the Libero synthesis configuration option values.
01267958, 01337923	PF_SOC: MSS configurator MSS_DDR x16 with ECC generates incorrect ECC bit port names.	PolarFire SoC MSS Configurator has been updated to separate the ECC ports from the DQ bus. For more information, see the PolarFire SoC MSS Technical Reference Manual.
1281380	View Device Status does not show System Controller Suspend Mode status for PolarFire SoC devices.	View Device Status now displays the status of System Controller Suspend Mode under security information.
1282955	SmartDebug ddc enhancement - user control of keys in a ddc file.	See section SmartDebug: DDC File Includes Security Component Options DPK, UPK1, and Display DPK (UPK1) in Smart Debug.
1298496	Internal error in the m_generic.exe executable file.	Resolved this issue by fixing the inconsistency in the vector width of the component ARI1.
1297700	SmartTime reports clock jitter for hold analysis with set_external_check constraint.	Ignore clock jitter for paths with external hold constraints (set_external_check).
1292230	RTG4: Timing path is not analyzed properly.	Ignore clock jitter during hold check when launching and capturing flip-flops are the same instance.
1303359	Input ports are left floating in the SynplifyPro technology view.	Resolved clocking-related issues due to VHDL clk'event constructs for memory and register.
1315776	RTG4: Input jitter calculation does not appear in SmartTime.	Timing constraint check reports an error when the clock name used with set_input_jitter is incorrect.
1324173	RTG4: Incomplete DRC error message.	DRC check shows the complete error message when a sequential element is connected to a constant.
1329580	An issue in the design hierarchy occurs when using if-else-generate statements in VHDL.	Support has been added for if-else-generate statements in VHDL.
1313443	The option Keep MSS in operational state during programming for IAP in Advanced Options for SPI File exports an incorrect bitstream.	Exported bitstream now sets the Keep MSS in operational state during programming for IAP option correctly based on user selection.
1338113	SmartTime in v2023.2 crashes in customer designs when an incorrectly generated clock constraint results in a 0% or 100% duty cycle.	Resolved this issue.
1354365	PF_CCC: Glitch observed on PLL Lock signal and PLL output clock when restarting the PLL reference clock.	The PolarFire CCC/PLL simulation model has been updated to remove the glitch on PLL LOCK.
1342334	An issue with the Constraint coverage report generated by the Libero tool has been observed.	Improved constraint coverage report by accounting for IP constant outputs.
493642-2790842682	RTG4: Dynamic ODT reserves three I/Os per bank that are not needed.	See section Increase the I/O Capacity per Bank in Designs with Dynamic ODT.
1369888	RTG4: Invalid error code is generated during programming.	Added a valid error code to display proper error message in case of corrupted or noisy bitstream.
1336193	Inconsistent Libero LE/CHKSUM results.	Resolved an issue in the I/O register combining order.
1209218	PF_IOD_CDR: CorePCS Code Errors with PolarFire IOD CDR at lower speed.	See section PF_IOD_CDR: EYE_MONITOR_WIDTH Parameter Selection.
1384406	When programming RTG4 with System Controller Suspend Mode enabled, subsequent JTAG actions behave differently when using different types of programmers.	The wait time has been increased near the end of programming actions, which resolved the race condition issue with the system controller detecting TRSTB as high and exiting Suspend Mode.
1335497	The IBIS model of the MPF300T-FCVG484T2 device is not generated using the Libero SoC tool.	Added the MPF300T-FCVG484T2 die package combination in the supported die-pkg list.
493642-2790842682, 01336396	RTG4 dynamic ODT usage reducing number of I/O pins per bank.	See section Increase the I/O Capacity per Bank in Designs with Dynamic ODT.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2024.1 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 3-7. Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary	Resolution
Revised the Libero SoC Simulation Library User Guide to improve the experience for users designing with Microchip FPGAs.	Added the following note in the Libero SoC Simulation Library User Guide: By default, the simulation tool other than the ModelSim Pro ME performs design optimization during simulation that can impact the visibility into simulation artifacts such as design objects and input stimulus. This is typically helpful in reducing simulation runtime for the complex simulations, using verbose, self-checking testbenches. However, the default optimizations might not be appropriate for all simulations, especially in cases where you expect to graphically inspect the simulation results using the wave window. To address issues caused by this optimization, you must add appropriate commands and related arguments during simulation to restore visibility into the design. For tool-specific commands, see the documentation of the simulator in-use.
SmartFusion2/IGLOO2/PolarFire/PolarFire SoC/RTPF softTMR-FF report	See section Synplify Pro ME and Identify ME Tools Upgraded to V-2023.09M.
Synplify TMR report misses reporting arch level tmr	See section Synplify Pro ME and Identify ME Tools Upgraded to V-2023.09M.
PolarFire Libero SoC 2022.3 TMR Report ERROR	See section Synplify Pro ME and Identify ME Tools Upgraded to V-2023.09M.
In RTG4, the FDDR_INIT core fractional clock frequency is not supported in batch.	See RTG4FDDRC_INIT core update in Table 2-1 in section Core Enhancements and Upgrades.
Using simulation memory initialization does not work properly when used through the graphical user interface.	Memory configurators and related documents have been updated to handle and explain the initialization of memory.