4.5 New Silicon Features and Enhancements

Libero SOC v2023.2 introduces standalone initialization of the PCIe and XCVR blocks to generate CoreABC instructions for initializing the TX PLL, PCIe controller, and XCVR quad registers.

Currently, the device system controller performs automatic device initialization of volatile configuration registers after power-up or DEVRST_N release. This behavior allows users to set up design-specific automatic initialization of these hard IP blocks in the device, using data stored in internal secure non-volatile memory (sNVM).

Introducing standalone initialization additionally allows designers to perform on-demand configuration to mitigate possible radiation-induced upsets in the volatile configuration registers of these blocks. This solution uses CoreABC v4.0 with fault-tolerant features enabled to reconfigure the TX PLL, PCIe controller, and XCVR quad registers whenever errors are detected by the user design, thus returning to the desired operational state. Libero SoC v2023.2 automatically generates the CoreABC assembly code necessary to re-initialize these blocks back to the user-desired configuration, allowing them to return to the desired operating state.

The following three additional presets are available for Transceiver Interface configurator (PF_XCVR_ERM) and Transmit PLL configurator (PF_TX_PLL) for ease of use when configuring the following interfaces:

• RXAUI
• JESD204B Transmitter Link with DAC39J84
• JESD204B Receiver Link with AD9680

The first two presets will also be added in the Transmit PLL configurator (PF_TX_PLL).

The new PLL solution for PF_CCC has increased accuracy in the non-integer mode and improves VCO computation accuracy.

Starting with Libero SoC v2023.2, design-specific LVDS receiver IBIS models for VCM = LOW and VCM = MID configuration option will be generated for PolarFire devices. Updated generic models are also available on the web.

Starting with Libero SoC v2023.2, the RTG4 LSRAM ECC simulation provides a way for users to control the assertion of ECC flags according to their address and data bit selections. Users must provide the address for which they want an ECC flag along with data mask bits, which will determine whether to assert SB_CORRECT or DB_DETECT flags. For more information, see RTG4 FPGA Fabric User Guide.

The Init config report file has an additional section that reports information about the Serdes RefClk I/Os. These are dedicated I/Os and are not the same as regular I/Os. The Generate FPGA Array Data step creates this report in multiple formats, such as <top>_init_config.txt and <top>_init_config.xml, containing information about the RefClk I/Os.