1.4.1 PolarFire®, PolarFire SoC, RT PolarFire, and RT PolarFire SoC

This section describes enhancements to the PolarFire® transceiver simulation model in Libero® SoC v2026.1.

Libero® SoC v2026.1 adds post-layout simulation support for statically delayed PolarFire® IOD resources. This support does not apply to dynamically trained PF_IOD interfaces. In this release, only post-layout gate-level functional simulation behavior is supported for the statically delayed PF_IOD resources. The PF_IOD external timing check arcs have been removed to prevent currently unsupported back-annotated timing simulation results through the IOD.

Libero® SoC v2026.1 enables PF_IOD post-layout simulation with startup or initial tap values. This enhancement allows customers to more accurately simulate IOD delay behavior based on configured initial conditions.

Libero® SoC v2026.1 improves the PF_IOD_OCTAL_DDR configurator by displaying the rounded frequency for the CCC PLL Output 3 clock divider label. This update improves readability and helps users better understand the generated clock configuration.

Libero® SoC v2026.1 enhances PF_IOD_GENERIC_RX configuration guidance for data rate versus fabric clock speed. This update helps customers configure receive interfaces with improved awareness of valid data-rate and fabric-clock relationships.

Libero® SoC v2026.1 updates the PF_XCVR configurator to support the Global (shared) clock option for applicable TX and RX clock configurations where both global and regional clock ports are exposed. This allows supported designs to use the quad's shared global clock output while retaining regional clock outputs for other lane clocks, subject to the device limitation of one global clock output to the fabric per quad.

Libero® SoC v2026.1 updates PF_PCIE UIC initialization for PCIe configurations using -6 dB de-emphasis. This enhancement improves support for PCIe designs that require this de-emphasis setting.

Libero® SoC v2026.1 updates the PF_Crypto tooltip and parameter-description guidance to clarify the supported AHB clock frequency ranges for embedded DLL configurations. The embedded DLL must be enabled when the AHB clock frequency is greater than or equal to 125 MHz, and disabled when the AHB clock frequency is less than or equal to 70 MHz; AHB clock frequencies greater than 70 MHz and less than 125 MHz are not supported for this configuration.

Libero® SoC v2026.1 now reports a warning when I/O Calibration is not enabled for banks using memory interfaces. This warning helps customers identify potential DDR configuration issues earlier in the design flow.

Libero® SoC v2026.1 adds pre-placement checks for PolarFire® IOD resources. This enhancement helps identify IOD placement issues earlier in the design flow and improves implementation predictability for supported designs.

Libero® SoC v2026.1 improves routability for designs where global signals drive wide-mux structures. This enhancement helps improve routing robustness for applicable PolarFire designs.

Libero® SoC v2026.1 adds a Design Rule Check to validate that the IP pin CLK_FROM_RCOSC_160MHZ is driven by the RC Oscillator. This check helps users identify invalid clock-source connections early in the design flow.

Libero® SoC v2026.1 expands Silver license support for the following PolarFire® device/package combinations:

• MPF300TS-1FCG1152I
• MPF200TC:
  • FCG1152I
  • FCG1152E
  • FCVG484E