2.3.3 ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7V
The ADC INL performance degrades if CLKADC > 1.5 MHz and ADCn.CALIB.DUTYCYC set to ‘0’ for VDD < 2.7V.
Work Around
None.
Affected Silicon Revisions
Rev. A |
X |
The ADC INL performance degrades if CLKADC > 1.5 MHz and ADCn.CALIB.DUTYCYC set to ‘0’ for VDD < 2.7V.
None.
Rev. A |
X |
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.