Product Description

The PCIe 5.0 PHY consists of a Physical Medium Attachment (PMA), also known as SerDes, and a raw Physical Coding Sublayer (PCS). NVMe 5016 supports up to four lanes, with both x4 and 2x2 bifurcation configurations available.

The PHY supports a source synchronous clocking interface on both the transmit (TX) and receive (RX) datapaths, allowing the clock signal to be transmitted alongside the data signal. The TX parallel data and TX clock input are synchronized with each other. On the receive side, the RX parallel data is output synchronized with an RX clock that is recovered from the corresponding serial data stream for each lane.