3.2.2 Implementation Example

The SAMA7D65 MPU is available in a single 14x14 mm², 0.65 mm pitch, 343-ball TFBGA package, optimized for standard class PCB layout (down to four layers).

Implementing the MPU on a PCB requires a stack-up of at least four layers. A 4-layer stack-up example with line width and clearances is provided in the following figure.

Figure 3-3. 4-Layer Stack-up

For PCB designs in which EMC compliance is a concern, it is recommended to use a stack-up of six layers or more. The stack-up example below allows for high-speed traces to be placed on the inner signal layers 3 and 4, while the rest of the layers can be assigned to low-speed signals, ground or power.

Figure 3-4. 6-Layer Stack-up

If the required line characteristic impedance values are met, similar eight-layer (or more) stack-ups can be used.

These stack-ups were chosen because they can provide all the required impedances by using minimum of 100 µm-wide traces.

The minimum trace width is 100 µm (~4 mil), which is relatively standard nowadays for PCB manufacturers. This also ensures that the routing does not take much space on the board.