Connect the external memory chosen as
required in the table “I/O Lines Usage vs. Operating Mode” in the Universal DDR Memory
Controller (UDDRC) chapter of the SAMA7D6 Series data
sheet.
The DDR_ZQ calibration cell input should
be connected to ground with a 240 Ω ±1% resistor. The same resistor value is used
regardless of the chosen memory device type.
Use a filtered simple voltage divider
made with two 1 kΩ ±1% resistors to generate the DDR_VREF voltage from the VDDIODDR
rail. DDR_VREF should be half the voltage of VDDIODDR and should be connected to the
DDR_VREF pin of the MPU.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
