4.2.2 JTAG Physical Interface

The JTAG interface consists of a four-wire Test Access Port (TAP) controller that is compliant with the IEEE® 1149.1 standard. The IEEE standard was developed to provide an industry-standard way to efficiently test circuit board connectivity (Boundary Scan). Microchip AVR and SAM devices have extended this functionality to include full Programming and On-chip Debugging support.

Figure 4-1. JTAG Interface Basics