24.8.9 Counter Value in COUNT32 mode (CTRLA.MODE
= 0)
Note:
This register is
read-synchronized and write-synchronized: SYNCBUSY.COUNT must be checked to
ensure the COUNT register synchronization is complete.
This register must be written with 32-bit accesses only.
Prior to any read access, this register must be synchronized by the user
by writing the COUNT Read Synchronization Enable bit in the Control A
register (CTRLA.COUNTSYNC = 1).
Name:
COUNT
Offset:
0x18
Reset:
0x00000000
Property:
PAC Write-Protection,
Write-Synchronized
Bit
31
30
29
28
27
26
25
24
COUNT[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
COUNT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – COUNT[31:0] Counter
Value
These bits define
the value of the 32-bit RTC counter in mode 0.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
