44.8.3 Configuration A

Name: CFGA
Offset: 0x02
Reset: 0x0000
Property: PAC Write-Protection, Enable-protected

Bit 15141312111098 
 DIVREF        
Access R/W 
Reset 0 
Bit 76543210 
 REFNUM[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 15 – DIVREF Divide Reference Clock. Only available on SAM C20/C21 N variants.

Divides the reference clock by 8

ValueDescription
0 The reference clock is divided by 1.
1 The reference clock is divided by 8.

Bits 7:0 – REFNUM[7:0] Number of Reference Clock Cycles

Selects the duration of a measurement in number of CLK_FREQM_REF cycles. This must be a non-zero value, i.e. 0x01 (one cycle) to 0xFF (255 cycles).