34.6.8 Interrupts

The CAN has the following interrupt sources:

  • Access to Reserved Address
  • Protocol Errors (Data Phase / Arbitration Phase)
  • Watchdog Interrupt
  • Bus_Off Status
  • Error Warning & Passive
  • Error Logging Overflow
  • Message RAM Bit Errors (Uncorrected / Corrected)
  • Message stored to Dedicated Rx Buffer
  • Timeout Occurred
  • Message RAM Access Failure
  • Timestamp Wraparound
  • Tx Event FIFO statuses (Element Lost / Full / Watermark Reached / New Entry)
  • Tx FIFO Empty
  • Transmission Cancellation Finished
  • Timestamp Completed
  • High Priority Message
  • Rx FIFO 1 Statuses (Message Lost / Full / Watermark Reached / New Message)
  • Rx FIFO 0 Statuses (Message Lost / Full / Watermark Reached / New Message)

Each interrupt source has an interrupt flag associated with it. The interrupt flag register (IR) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing ‘1’ or disabled by writing ‘0’ to the corresponding bit in the interrupt enable register (IE). Each interrupt flag can be assigned to one of two interrupt service lines.

An interrupt request is generated when an interrupt flag is set, the corresponding interrupt enable is set, and the corresponding service line enable assigned to the interrupt is set. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the service line is disabled, or the CAN is reset. Refer to IR34.8.16 Interrupt for details on how to clear interrupt flags. All interrupt requests from the peripheral are sent to the NVIC. The user must read the IR register to determine which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated.