33.10.2 Control B

Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
      ACKACTCMD[1:0] 
Access R/WWW 
Reset 000 
Bit 15141312111098 
       QCENSMEN 
Access R/WR/W 
Reset 00 
Bit 76543210 
          
Access  
Reset  

Bit 18 – ACKACT Acknowledge Action

This bit defines the I2C host's acknowledge behavior after a data byte is received from the I2C client. The acknowledge action is executed when a command is written to CTRLB.CMD, or if Smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.

This bit is not enable-protected.

This bit is not write-synchronized.

ValueDescription
0 Send ACK.
1 Send NACK.

Bits 17:16 – CMD[1:0] Command

Writing these bits triggers a host operation as described below. The CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in Host Read mode. In Host Write mode, a command will only result in a repeated Start or Stop condition. The CTRLB.ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered.

Commands can only be issued when either the Client on Bus Interrupt flag (INTFLAG.SB) or Host on Bus Interrupt flag (INTFLAG.MB) is '1'.

If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a repeated start followed by transmission of the new address.

Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP).

Table 33-4. Command Description
CMD[1:0] Direction Action
0x0 X (No action)
0x1 X Execute acknowledge action succeeded by repeated Start
0x2 0 (Write) No operation
1 (Read) Execute acknowledge action succeeded by a byte read operation
0x3 X Execute acknowledge action succeeded by issuing a Stop condition

These bits are not enable-protected.

Bit 9 – QCEN Quick Command Enable

This bit is not write-synchronized.

ValueDescription
0 Quick Command is disabled.
1 Quick Command is enabled.

Bit 8 – SMEN Smart Mode Enable

When Smart mode is enabled, acknowledge action is sent when DATA.DATA is read.

This bit is not write-synchronized.

ValueDescription
0 Smart mode is disabled.
1 Smart mode is enabled.