33.8.8 Address

Name:	ADDR
Offset:	0x24
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected


Bit	31	30	29	28	27	26	25	24
						ADDRMASK[9:7]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	23	22	21	20	19	18	17	16
	ADDRMASK[6:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TENBITEN					ADDR[9:7]
Access	R/W					R/W	R/W	R/W
Reset	0					0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDR[6:0]							GENCEN
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 26:17 – ADDRMASK[9:0] Address Mask

These bits act as a second address match register, an address mask register or the lower limit of an address range, depending on the CTRLB.AMODE setting.

Bit 15 – TENBITEN Ten Bit Addressing Enable

Value	Description
0	10-bit address recognition disabled.
1	10-bit address recognition enabled.

Bits 10:1 – ADDR[9:0] Address

These bits contain the I²C client address used by the client address match logic to determine if a host has addressed the client.

When using 7-bit addressing, the client address is represented by ADDR[6:0].

When using 10-bit addressing (ADDR.TENBITEN=1), the client address is represented by ADDR[9:0]

When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate whether it is a read or a write transaction.

Bit 0 – GENCEN General Call Address Enable

A general call address is an address consisting of all-zeroes, including the direction bit (host write).

Value	Description
0	General call address recognition disabled.
1	General call address recognition enabled.