26.6.4.3 Interrupt Pin Debouncing (only available on SAM C20/C21 N variants)
The external interrupt pin (EXTINT) edge detection can use a debouncer to improve input noise immunity. When selected, the debouncer can work in the synchronous mode or the asynchronous mode, depending on the configuration of the ASYNCH.ASYNCH[x] bit for the pin. The debouncer uses the EIC clock as defined by the CTRLA.CKSEL bit to clock the debouncing circuitry. The debouncing time frame is set with the debouncer prescaler DPRESCALER.PRESCALERm, which provides the low-frequency clock tick that is used to reject higher frequency signals.
The Debouncing mode for the EXTINT x pin can be selected only if the Sense bits in the configuration register (CONFIGn.SENSEx) are set to RISE, FALL or BOTH. If the debouncing mode for the EXTINT x pin is selected, the filter mode for that pin (CONFIGn.FILTENx) can not be selected.
The debouncer manages an internal “valid pin state” that depends on the external interrupt (EXTINT) pin transitions, the debouncing mode, and the debouncer prescaler frequency. The valid pin state reflects the pin value after debouncing. The external interrupt (EXTINT) pin is sampled continously on EIC clock. The sampled value is evaluated on each low-frequency clock tick to detect a transitional edge when the sampled value is different of the current valid pin state. The sampled value is evaluated on each EIC clock when DPRESCALER.TICKON = 0 or on each low frequency clock tick when DPRESCALER.TICKON = 1, to detect a bounce when the sampled value is equal to the current valid pin state. Transitional edge detection increments the transition counter of the EXTINT pin, while bounce detection resets the transition counter. The transition counter must exceed the transition count threshold as defined by the DPRESCALER.STATESm bitfield. In the synchronous mode the threshold is 4 when DPRESCALER.STATESm = 0, or 8 when DPRESCALER.STATESm = 1. In the asynchronous mode the threshold is 4.
The valid pin state for the pins can be accessed by reading the PINSTATE register for both synchronous or asynchronous debouncing mode.
Synchronous edge detection: In this mode the external interrupt (EXTINT) pin is sampled continously on the EIC clock.
- A pin edge transition will be validated when the sampled value is consistently different of the current valid pin state for 4 (or 8 depending on bit DPRESCALER.STATESm) consecutive ticks of the low frequency clock.
- Any pin sample, at the low-frequency clock tick rate, with a value opposite to the current valid pin state will increment the transition counter.
- Any pin sample, at EIC clock rate (when DPRESCALER.TICKON = 0) or the low-frequency clock tick (when DPRESCALER.TICKON = 1), with a value identical to the current valid pin state will return the transition counter to zero.
- When the transition counter meets the count threshold, the pin edge transition is validated and the pin state PINSTATE.PINSTATE[x] is changed to the detected level.
- The external interrupt flag (INTFLAG.EXTINT[x]) is set when the pin state PINSTATE.PINSTATE[x] is changed.
In the Synchronous Edge Detection mode, the EIC clock is required. The Synchronous Edge Detection mode can be used in Idle and Standby Sleep modes.
- Any edge detection that indicates a transition from the current valid pin state will immediately set the valid pin state PINSTATE.PINSTATE[x] to the detected level.
- The external interrupt flag (INTFLAG.EXTINT[x] is immediately changed.
- The edge detector will then be idle until no other rising or falling edge transition is detected during 4 consecutive ticks of the low-frequency clock.
- Any rising or falling edge transition detected during the idle state will return the transition counter to 0.
- After 4 consecutive ticks of the low-frequency clock without bounce detected, the edge detector is ready for a new detection.
In this mode, the EIC clock is requested. The asynchronous Edge Detection mode can be used in Idle and Standby Sleep modes.