16.4 Signal Description
| Signal Name | Type | Description |
|---|---|---|
| GCLK_IO[7:0] | Digital I/O |
Clock source for Generators when input Generic Clock signal when output |
Note:
- One signal can be mapped on several pins.
- Each GCLK_IO[x] signal is connected to the related Generic Clock Generator x, for x in [7:0]. However,GCLK_IO[8] does not exist, so the Generic Clock Generator 8 is not connected to an external pin.