28.6.5 PORT Access Priority

The PORT is accessed by different systems:

  • The ARM® CPU through the ARM® single-cycle I/O port (IOBUS)

  • The ARM® CPU through the high-speed matrix and the AHB/APB bridge (APB)

  • EVSYS through four asynchronous input events

The CPU local bus (IOBUS) is an interface that connects the CPU directly to the PORT. It is a single-cycle bus interface, which does not support wait states. It supports 8-bit, 16-bit and 32-bit sizes.

This bus is generally used for low-latency operation. The Data Direction (DIR) and Data Output Value (OUT) registers can be read, written, set, cleared or be toggled using this bus, and the Data Input Value (IN) registers can be read.

Since the IOBUS cannot wait for IN register resynchronization, the Control register (CTRL) must be configured to continuous sampling of all pins that need to be read via the IOBUS in order to prevent stale data from being read.

Note: Refer to the Product Mapping chapter for the PORT IOBUS address.

The following priority is adopted:

  1. ARM® CPU IOBUS (No wait tolerated).
  2. APB.
  3. EVSYS input events, except for events with EVCTRL.EVACTn = OUT, where the output pin follows the event input signal, independently of the OUT register value.
Note: One clock cycle latency can be observed on the APB access in case of concurrent PORT accesses.

For input events that require different actions on the same I/O pin, refer to 28.6.4 Events