22.6.3.6 Sampling Mode

The Sampling Mode is a low-power mode where the BODVDD is being repeatedly enabled on a sampling clock’s ticks. The BODVDD will monitor the supply voltage for a short period of time and then go to a low-power disabled state until the next sampling clock tick.

Sampling mode is enabled in Active mode for BODVDD by writing the ACTCFG bit (BODVDD.ACTCFG=1). Sampling mode is enabled in Standby mode by writing to the STDBYCFG bit (BODVDD.STBYCFG=1). The frequency of the clock ticks (F_clksampling) is controlled by the Prescaler Select bit groups in the BODVDD register (BODVDD.PSEL).

F_{c l k s a m p l i n g} = \frac{F_{c l k p r e s c a l e r}}{2^{(PSEL + 1)}}

The prescaler signal (F_clkprescaler) is a 1.024 kHz clock, output by the 32.768 kHz Ultra Low Power Oscillator OSCULP32K.

As the sampling clock is different from the APB clock domain, synchronization among the clocks is necessary. See also 22.6.5 Synchronization.