24.10.1 Control A in COUNT16 mode (CTRLA.MODE=1)

Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 15141312111098 
 COUNTSYNC   PRESCALER[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
     MODE[1:0]ENABLESWRST 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 15 – COUNTSYNC COUNT Read Synchronization Enable

The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register.

This bit is not enable-protected.

ValueDescription
0 COUNT read synchronization is disabled
1 COUNT read synchronization is enabled

Bits 11:8 – PRESCALER[3:0] Prescaler

These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized.
ValueNameDescription
0x0 OFF CLK_RTC_CNT = GCLK_RTC/1
0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1
0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2
0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4
0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8
0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16
0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32
0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64
0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128
0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256
0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512
0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF - Reserved

Bits 3:2 – MODE[1:0] Operating Mode

This field defines the operating mode of the RTC. This bit is not synchronized.
ValueNameDescription
0x0 COUNT32 Mode 0: 32-bit counter
0x1 COUNT16 Mode 1: 16-bit counter
0x2 CLOCK Mode 2: Clock/calendar
0x3 - Reserved

Bit 1 – ENABLE Enable

Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
ValueDescription
0 The peripheral is disabled
1 The peripheral is enabled

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete.

ValueDescription
0 There is not reset operation ongoing
1 The reset operation is ongoing