15.7 Clocks after Reset

On any reset the synchronous clocks start to their initial state:

  • OSC48M is enabled and divided by 12
  • GCLK_MAIN uses OSC48M as source
  • CPU and BUS clocks are undivided

On a power reset the GCLK starts to their initial state:

  • All generic clock generators disabled except:
    • The generator 0 (GCLK_MAIN) using OSC48M as source, with no division
  • All generic clocks disabled

On a user reset the GCLK starts to their initial state, except for:

  • Generic clocks that are write-locked (WRTLOCK is written to one prior to reset)

On any reset the clock sources are reset to their initial state except the 32.768 kHz clock sources which are reset only by a power reset.