2.2 ADC Clock Divider Value

ADCLK register will be loaded with odd-numbered values (e.g., 0x01, 0x03, 0x05, etc.) for accurate ADC results. The ADC Clock divider is only available if FOSC is selected as the ADC Clock source, as this is not applicable when using ADCRC as the source.

The formula below gives the ADC Clock frequency:

A D C ⁢   C l o c k ⁢ f r e q u e n c y =   F o s c 2 * ( n + 1 )

Where n is the ADCLK value.

Table 2-1 mentions the recommended FOSC division values:

Table 2-1. Recommended FOSC Clock Divider Values
FOSC/4 FOSC/8 FOSC/12 FOSC/16 FOSC/20 FOSC/24 FOSC/28 FOSC/32
FOSC/36 FOSC/40 FOSC/44 FOSC/48 FOSC/52 FOSC/56 FOSC/60 FOSC/64