11.1 Application Implementation with AVR128DA64

The AVR DA family of microcontrollers has up to three instances of ZCD peripheral. In the 64-pin variants of the AVR DA devices, three ZCD instances are available. If all three ZCD instances are used for the phase sequence detection application, the phase loss can also be computed by the ZCD peripheral.

This section explains implementation of phase sequence detection for the three-phase supply using the AVR128DA64 microcontroller. Here in this implementation, TCA0 is used for scheduling the tasks every 500 μs; it is configured to generate an interrupt for every 500 μs. TCA1 is used for measuring the time in between two ZCD interrupts (i.e. phase-shift in-between the phases of three-phase input); it is configured to generate an overflow interrupt for 20 ms. ADC is used for reproducing the input signal on data visualizer (for demonstration); it is also used for three-phase RMS voltage measurement. The ADC is configured with 2 MHz ADC clock and 126.3 kHz (0.79 μs) sampling rate. SPI is used to integrate the waveform click module for generating the three-phase emulated signal; it is configured with Master mode, 6 MHz SPI clock, and data mode 2. The three ZCD instances are used for detecting the zero cross of three-phase input signal; they are configured with an interrupt on the rising edge signal. USART is used for communication between the host computer and application setup; it is configured for a baud rate of 230400.

Firmware Implementation

The phase sequence detection for the three-phase supply application firmware is split into six sections:
  • Initialization
  • Phase reversal detection logic
  • Phase loss detection logic
  • RMS voltage measurement
  • Task scheduler
  • Emulator functionalities

The phase reversal detection and RMS voltage measurement are implemented as presented in the Application Firmware Implementation section. The single phasing or phase loss detection functionality is implemented using three ZCD instances, as the AVR128DA64 microcontroller comes with three ZCD instances.

The phases of the three-phase input signals L1, L2, and L3 are connected to three ZCD input, ZCD instances are configured to generate interrupt when the rising input signal voltage crosses the threshold voltage. Here, the 120° phase shift between the three signals can be determined seamlessly, as the three phases of the input signal are connected to the respective ZCD instances. Phase loss can be identified by monitoring the rising edges of the input signal in the expected time.

In each ZCD instance Interrupt Service Routine (ISR), the occurrence of zero-crossing interrupt on all the three ZCD instances is monitored to detect the phase loss event. The application flow diagram of phase loss detection is shown in Figure 11-1.

Figure 11-1. Logic Diagram of Phase Loss Detection Using Three ZCD’s

The application firmware of the phase sequence detector demo using AVR128DA64 is available to download from GitHub.

Note:
  1. The firmware is developed with the STK600 development board. The kit offers access to all device pins and several useful hardware functions, such as push buttons, LEDs, and DataFlash to create a complete system for prototyping and testing new designs.
  2. The AVR device connects to the STK600 using an innovative routing (STK600-RC064AVR-108) and socket (STK600-TQFP64-2) card sandwich system, which routes the signals from the device to the appropriate hardware.