Figure 51-144. Open Loop Gain
and Phase Bode Plot
Figure 51-145. Phase Margin
over Temperature and VDD
Figure 51-146. Phase Margin
over VDD and Temperature
Figure 51-147. Gain Bandwidth
Product over Temperature and VDD
Figure 51-148. Gain Bandwidth
Product over VDD and Temperature
Figure 51-149. PSRR over
Frequency and Temperature
Figure 51-150. Voltage Noise
Density for GND with CPON = 0
Figure 51-151. Slew Rate
Falling over VDD and Temperature
Figure 51-152. Slew Rate
Rising over VDD and Temperature
Figure 51-153. Output
Impedance over Frequency
Figure 51-154. Small-Signal
Non-Inverting Pulse Response
Figure 51-155. Large-Signal
Non-Inverting Pulse Response
Figure 51-156. Offset over
Temperature with VDD = 1.8V, VCM =
VDD /2 (Factory Calibrated Input Offset
Voltage)
Figure 51-157. Offset over
Temperature with VDD = 1.8V, VCM =
VDD /2 (Automatic Input Offset Voltage
Calibration)
Figure 51-158. Offset over
Temperature with VDD = 3.0V, VCM =
VDD /2 (Factory Calibrated Input Offset
Voltage)
Figure 51-159. Offset over
Temperature with VDD = 3.0V, VCM =
VDD /2 (Automatic Input Offset Voltage
Calibration)
Figure 51-160. Offset over
Temperature with VDD = 5.5V, VCM =
VDD /2 (Factory Calibrated Input Offset
Voltage)
Figure 51-161. Offset over
Temperature with VDD = 5.5V, VCM =
VDD /2 (Automatic Input Offset Voltage
Calibration)
Figure 51-162. Offset vs.
VCM and Temperature and VDD = 1.8V
(Factory Calibrated Input Offset Voltage)
Figure 51-163. Offset vs.
VCM and Temperature and VDD = 1.8V
(Automatic Input Offset Voltage Calibration)
Figure 51-164. Offset vs.
VCM and Temperature and VDD = 3.0V
(Factory Calibrated Input Offset Voltage)
Figure 51-165. Offset vs.
VCM and Temperature and VDD = 3.0V
(Automatic Input Offset Voltage Calibration)
Figure 51-166. Offset vs. VCM
and Temperature and VDD = 5.5V (Factory Calibrated
Input Offset Voltage)
Figure 51-167. Offset vs.
VCM and Temperature and VDD = 5.5V
(Automatic Input Offset Voltage Calibration)
Figure 51-168. PSRR at DC
over VDD and Temperature
Figure 51-169. CMRR at DC
over VDD and Temperature
Figure 51-170. Open Loop Gain
over VDD and Temperature
Figure 51-171. Open Loop Gain
over Temperature and VDD
Figure 51-172. Output Sinking
Short Circuit Current over VDD and
Temperature
Figure 51-173. Output
Sourcing Short Circuit Current over VDD and
Temperature
Figure 51-174. VOH
over Temperature and Load Current
Figure 51-175. VOL
over Temperature and Load Current
Figure 51-176. Turn-On Time
over VDD and Temperature