33.5.9 ASI System Status
| Name: | ASI_SYS_STATUS |
| Offset: | 0x0B |
| Reset: | 0x01 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BDEF | ERASEFAIL | SYSRST | INSLEEP | PROGSTART | UROWSTART | BOOTDONE | LOCKSTATUS | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Bit 7 – BDEF Boot Sequence Done or Chip Erase Failed
1’ if the chip erase has failed (ERASEFAIL bit is
‘1’) or the boot sequence is complete (BOOTDONE bit is
‘1’).Bit 6 – ERASEFAIL Chip Erase Key Failed
1’ if the chip erase has failed. This bit is set to
‘0’ on Reset. A Reset held from the ASI Reset Request
(ASI_RESET_REQ) register will also affect this bit.Bit 5 – SYSRST System Reset Active
When this bit is set to ‘1’, there is an active
Reset on the system domain. When this bit is set to ‘0’, the
system is not in the Reset state.
This bit is set to ‘0’ on read.
A Reset held from the ASI_RESET_REQ register will also affect this bit.
Bit 4 – INSLEEP System Domain in Sleep
When this bit is set to ‘1’, the system domain is
in Idle or deeper sleep mode. When this bit is set to ‘0’, the
system is not in any sleep mode.
Bit 3 – PROGSTART Start NVM Programming
When this bit is set to ‘1’, NVM programming can start from the
UPDI.
When the UPDI is done, the system must be reset through the ASI Reset Request (ASI_RESET_REQ) register.
Bit 2 – UROWSTART Start User Row Programming
When this bit is set to ‘1’, user row programming can start from
the UPDI.
When the User Row data have been written to the RAM, the UROWDONE bit in the ASI_SYS_CTRLA register must be written.
Bit 1 – BOOTDONE Boot Sequence Done
This bit is set to ‘1’ when the CPU is done with the boot
sequence. The UPDI will not have access to the ACC layer until this bit is set
to ‘1’.
Check also that SYSRST is ‘0’ before proceeding.
Bit 0 – LOCKSTATUS NVM Lock Status
When this bit is set to ‘1’, the device is locked.
If a chip erase is done, and the lock bits are set to ‘0’, this
bit will be read as ‘0’.